Method of work for generating rigid-flex design

Has anyone used Kicad for a rigid-flex design? Can anyone suggest a method of work, such as layer naming, layer alignment, etc?
My conceptual design is a flexible circuit with a smaller 1 layer (copper on one side) rigid pcb adhered to the top of flex circuit. The top copper of the rigid board would be connected to the bottom copper of the flex circuit with a plated through hole. Note that there are only 3 layers of copper, not the typical 4. Since my top, rigid copper does not need to connect to the inner flex copper, and no blind vias, it should be easier to indicate plate through. However, I will have smd parts on all “exposed” copper layers. This is my proposed design:

However, Kicad does not let me rename or rearrange the layers. All the copper layers are in the middle of the board. For example, these are Kicad 4 layer arrangements:


You can easily enough simply skip an unused layer, to eg only plot 3 working layers

That’s where the issues will arise.
How will these assemble ? They need to paste, then place.
I presume they have some fixture that allows flex to paste-screen ok, on both sides, and that P&P is managed as a 2 layer process ?

Present KiCad release has issues around PAD Stack handling, for example a possible useful stack like

(pad 1 smd oval (at -3.5814 -1.2446 90) (size 2.9972 1.27) (layers In1.Cu F.Paste F.Mask)
  (net 19 CLKIN))

will simply crash KiCad :frowning:

You can import this, which gives SMD pad on inner layers

(pad 1 smd oval (at -3.5814 -1.2446 90) (size 2.9972 1.27) (layers *.Cu F.Paste F.Mask)
  (net 19 CLKIN))
(pad 1 smd circle (at -3.5814 -1.2446 90) (size 0 0) (layers F.Cu))
(pad 1 smd circle (at -3.5814 -1.2446) (size 0 0) (layers B.Cu))

That routes fine on In1,Cu, but unlike Paste Layers, which will trump Copper-clone-copies, the explicit user define of F.Cu fails to trump *.Cu, and you instead get smd copper copies on all layers.

How tight is the layout ?
One workaround is to do the design like a 2 layer one, which will manage stacks fine and connectivity checks, but you end up with a ‘unused’ footprint copy of FR4.Top, on the Flex.Top.
This is unused and becomes invisible when under the FR3

Another possible pathway is to fork the design and manage flex as a 2L design, and FR4 as a separate Top-only design, probably with a connector-row used as vias, (or special via-parts) to manage the boundary, that is carefully fixed in both designs. A script could check they still align after changes.
More of a pain, but you do get more routing room.


It’s been a long time since I have seen one of these. We used to use them with components on the rigid part only, presumably mounting smd on a flexible was frowned upon at the time

Good point, I would be quite wary about any surface mount on flex. Many parts would not tolerate that.
Resistors are intolerant of any flex, small and simple gull wing parts probably more so, but I do recall a field failure issue on even 1.6mm PCB, where a gland nut over-tighten flexed the PCB by just enough to have a SOT23 lead ‘stress release’ from the solder for intermittent results.
Fix was to fine tune the gland mechanics, to totally remove any flex effects.

The rigid part is a normal even number of layers PCB, take a look on Google for “rigid flex pcb” and you will see many examples up to 12 layer, where the flexi is just a tail for connection

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Makes sense - if the Op can manage that, then KiCad PCB should be able to handle the stackups ok.

I’ve done some checks, and if you really do need to ‘push’ a few pad shapes onto an inner flex layer, (possibly microswitch or similar) you can workaround by using a spare layer like F.Adhes and then OR the Gerber plots.
Care is needed, eg Microvia to preserve Electrical tests, and the real In1 pad is missing in this patch, so Fill inner is not possible, and clearance inner is not properly checked, but for a few parts, that may be tolerable.

Yes, smd components on flex is not common in a google search but it is done. (Think flexible LED strips, although these are typically flex only during install vs active flex) In fact I did this in a similar project. In my application, the amount of flex when is use was very minimal, and its geometry is such that the flexing happens where there are no components.

Even if I only had smd parts on the top of rigid pcb, it would still seem a challenge to implement this using Kicad. Thanks!

This was my initial thought and probably leaning towards. Here’s a very informative thread on mezzanine (daughter board) implementation that has some useful ideas but still would not work 100% for a rigid flex.

Looking at some of the images from Google, the rigid is the board and the flexi tail is a part with a footprint.

I updated the diagram by numbering the parts to make discussion easier
Question for both @PCB_Wiz and @davidsrsb : Since your feedback, I’ve been re-thinking my design. Would doing this in Kicad be any easier if I only have smd parts on the top of rigid pcb copper and bottom flex copper? I think it would be doable without additional workarounds. My thought is that the footprints T.Cu and B.Bu would correspond to my FR4 Top Cu and Flex Bottom Cu respectively. My Flex Top Cu would correspond to Kicad In1.Cu. I could then omit the In2.Cu gerber when sending to Fab house.

My concern is that to to draw the flex only vias (PTH in the center of this diagram) would be a “buried via” according to Kicad. Does this somehow show up in the Gerber files and if so will this confuse the Fab house?

Certainly, this is easier to manage, as now SMD and Paste and Mask, are all ‘natural’.
It is also easier to Pick and Place. - and it will be more reliable.

Yes, I would suggest you plot this, but do not send. Check yourself to ensure there are no In2.Cu tracks :slight_smile:
(You can also search the kiCad_pcb file for In2.Cu I think )
Make a deliberate mistake, and confirm you can catch it.

You could also check the price diff for 2 layer FR4, as that could be quite a small adder.
You already have the material and plating ‘in the system’, and sometimes when we have asked for single-sided, they have removed copper from 2 sided boards, as that was all they stocked !

You can use microvia, which in KiCad has a start-end layer (meaning it is more accurately a buried via), however I doubt that is needed.
The typical Via has identical Pad Stacks on all layers, and my understanding of the FAB order for flex, is to make the FR4 in a frame, then profile route before laminate for the voids (but still with enough carrier material to keep things together, then laminate, and finally drill and plate.
Stack-up wise, that means any missing FR4 takes care of itself, however you could need to ask the FAB about drilling exposed (unsupported/floppy) flex, as I’d guess that may have issues.
ie any needed vias may be best, all thru the FR4, which you may be able to manage ?

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Thanks for this and other tips! I think this will work out great!

Really? I thought a typical Via would be only between two layers, not interconnecting 4 layers with a pad on each layer? So in my diagram above, the via on the right and left are not typical, since they only have pads on the top and bottom copper?

If you completely omit pads on inner layers, that opens a can of worms.

  • Copper pour now needs to become drill-aware as well, in order to avoid dead-shorts.
  • Shove and DRC also need to become drill-aware.
  • If you DO add a trace on an inner layer, what happens to annular ring handling ?
  • Some PCB houses complain if there is a Drill with no annular ring - too often that signals a mistake

I believe there is a place for allowing Vias to have a smaller inner pad size, but right now, kiCad does not support that. You can change the total sizes easily, so that is usually close enough.
I would also like to see F.Paste being valid on a via, & that is an enhancement request.

If you build and plot a 4 layer PCB, this line
(via (at 120.396 103.16) (size 1.5) (drill 0.8) (layers F.Cu B.Cu) (net 1))
will create 1.5 dia pads on In1,Cu & In2.Cu, ie you get ‘expected’ annular rings on all layers, and pour pulls back from those pads.

There is another class of via, called a buried via, and that has a start and end layer.
Some user-care of often needed to make sure the stack-up can actually be manufactured :slight_smile:
In KiCad PCB, the not-all-layers Vias are supported as

Micro Via - hint says Copper to nearest neighbour, small hole
Blind.Buried Via - more general case, of at least one outer copper not drilled

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Can you explain what manufacturability issues I am looking for other than the clearance issues you listed? Also, I am not even sure how to place a Via in Kicad with a pad on all 4 layers of a 4 layer board. When I place a Via it only allow me to select 2 layers… Top/Front and Bottom/Back layers.

The inner layers are implicit - try a 4 layer design, and plot, then load all layers into GerbView.

It was in relation to buried/blind vias, and those dictate boards are drilled and then plated, during the stack&glue phases.
Of course, you need care to ensure what pairings you ask for, can actually be achieved using multiple stack and glue passes, and the more steps the FAB needs, the more it will cost you…

Only really tight designs tend to use buried/blind vias, due to this cost-adder effect …

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I don’t know if I’m too late, but I found this site that has a lot of useful info on that
and a pdf guide

The final approach: 2 layer FR4 adhered to 2 layer flex. No vias in the flex portion. It turns out that the flex areas are only acting as “hinges” and don’t really need vias there. Also, to keep costs down, I will not have any blind or buried vias. All vias will go through all layers with copper connections only on layers needed. This will allow the the FR4 + flex to be drilled once after they are adhered together. This crowds things a bit on the top and bottom layers, but it is a good compromise to keep cost down.