You could make the exact same argument for not choosing “Absolute”. If there are no actual known issues, then advising people to select options that aren’t necessary creates unfounded folklore.
The Important thing is that the option should match between the gerbers and drill file.
For reference, this is the zip file I submitted to JLC. Timer-ST.zip (112.2 KB)
I’ll backup the project and remove the alignment targets. I need to keep them for any future toner transfer boards. Toner transfer is labor-intensive, but, much faster for testing a new board than getting it from China. I can make one in a few hours 
I guess that there is a human at JLC who does a final check before okaying the design, but one thing I and others have found with JLC is that it is best to avoid getting into any “customer support” type email because it gets confusing very quickly!
Can you put those targets on a different layer?
Not yet, I think I see the problem by comparing the drill files, I noticed you have some oval holes. There are different ways to specify that in the drill file. It appears JLC are rejecting the “Route mode”.
In your version, try selecting “Use alternate drill mode”.
Is it really so? If I remember correctly we have some boards from JLCPCB which have oval holes in drill files and I have used only “route command” in gerber generating. It’s of course possible that they have different software version now or something like that.
The last board I ordered from JLC had ovals, and I was pleasantly surprised to find they came out ok. Here is a side by side:
The left file is the OPs generated with v5.1.2 Route mode, the right is my v5.0.0 without route mode (I call it “drill drag”, not sure if there is an official term).
Oops sorry, I think that might be a red herring. In the OPs pictures
the ovals are shown OK.
It’s annoying that manufacturers have instructions for v4 (JLCPCB has even a link to a v3 instruction video!). I sent them a message asking to update the instructions for v5. Let’s see what happens. Most of the information there is of course relevant but the drill mode isn’t there at all, and it would be easier to see everying in correct places in the UI screenshots.
Bobc,
“Use alternate drill mode” Fixed the drill file problems!!! I now only have the “Edge cuts” warning which I’ve already learned Is not a real problem with JLC.
Now I need to start rolling back all of the other changes that I applied to this project.
Thank You VERY much for the help solving my JLC/KiCad problem.
Yes, I can confirm that adding the route mode to a drill file produces the warning message, even if the PCB displayed in the JLC viewer shows slots.
It could be the warning is spurious and they handle the route mode anyway, but it’s confusing. I admit I never looked much at the analysis results before, but relied on the images.
One other error that I should mention. I’d solved this before starting this thread. I had checked the b.silks layer because that was recommended by JLC. This was giving a warning. I found it was because I had nothing on that layer. Looks like the JLC checker can’t handle empty layer files.
This is, at least, a well-intentioned effort to prevent you from doing something stupid, and perhaps a valuable review of your efforts.
For decades, one of the unwritten assumptions about dealing with PCB fabricators has been “Don’t send them irrelevant information”. The fact that they found a file in your Gerber package that seemed to be for back-side silk implies that you want some back-side silk on your board. (In previous times, back-side silk was always an extra-cost option - and sometimes a VERY costly option. Nobody would deliberately send a back-side silk file unless they REALLY wanted back-side silk.) Since your back-side silk file appeared to be empty, it suggests an error on your part. E.g., did you send the wrong file? Does the file that seems to be for back-side silk actually describe some other layer, accidentally labeled as back-side silk? Was the genuine back-side silk file accidentally named something else in your Gerber package?
I would NOT complain to JLC about the squawk, but rather thank them for their diligence.
Dale
I understand and agree. It’s not a bug, it’s a feature. It would be nice if the warnings were less cryptic. I didn’t know why it was flagging the file until I looked at it and saw only some headers and no data. Then I realized that I’d submitted an empty layer.
I can’t complain. it’s amazing that I can get PCB’s this cheap and, they even do some checking of the data that I submit!
I’m doing a little tweaking on the board before I submit it. I found that my text size was at the lower limit of what JlC supports. I’m bumping up the size a little to be sure that it’s readable.
I’ll post an update when I get the boards back from JLC.
It’s of course better to go with larger if there’s room. But even with cheap techology 0.8mm high characters can be readable enough to help with manual soldering. We have to do it constantly because all our designs use 0402 components and many have “as small as possible” size constraints. If you go below their recommendation it’s good to give a note where you say that they shouldn’t care about the text quality.
I bumped the text size up to 1.2mm wherever I had the room. Looks like there should be no problem reading this if .8mm is usually readable. Text is important to my project. I have people that want to buy blank boards from me to more easily build this project. They’ll be hand soldered by people that may not be electronics experts. Nice clear text labels make populating the board much easier!
Is anyone reading this old enough to remember Heathkit? I built a bunch of these kits 30+ years ago. If you could read instructions and use a soldering iron, you could build a Heathkit. -
I’m trying to make this open source project as easy as a Heathkit.
I just noticed I wasn’t completely clear. 0.8mm is usually readable enough (possibly with a microscope which is needed for effecient 0402 soldering) to help in locating components. Not all characters are necessarily good enough themselves but can be understood when compared with surrounding components and their texts. It may not be 100% reliable if someone without previous knowledge about that board would try to locate every component. But it’s good enough for most purposes.
1.2mm is almost extravagant provided that they aren’t on top of vias etc.
JLC has a slightly better silkscreen than other cheap fabs, but starts to get blobby around 1mm. “B” and “8” can look very similar. So i wouldn’t go below 1mm, which should be legible by people with good vision in most cases.
Since I mainly use 0805/0603, I use a microscope anyway.
For texts that need to be clear and unambiguous, and by people with perhaps less than perfect vision, I use 1.5mm.
Another tip for JLC, is to put a text “JLCJLCJLCJLC” somewhere which they will use to put a serial number.
What’s the difference between “Use route command” and “Use alternate drill mode”?
As far as I can tell:
The Route command in Excellon drill files is G00, but it’s relatively new and not all CAM systems support it. Routes can then be done with a router bit.
An earlier method is to use G85 command which is supposed to work by drilling a series of overlapping holes, but manufacturers don’t like doing that as it breaks drill bits.
That makes sense. Sounds like router bits are preferred for oval holes. I expect to use JLCPCB again so that’s good to know.
