Controlled-impedance traces tend to be pretty wide - in my case based on a stack up provided by my fab, they need to be 0.295 mm with at least 1:1 clearance. So what I did is defined a dedicated “Highspeed” net class with 0.295/0.295 trace width/clearance. However in BGA breakout area where is not enough space between pins to have such large tracks with this clearance, so thinner traces need to be used (and it’s OK and recommended technique by chip manufacturers).
In Kicad pcbnew, I can make traces thinner for a part of it’s way, however clearance still comes from the netclass and I couldn’t find a way to change that, consequently pcbnew does not allow me to route traces unless I disable DRC, and I get a ton of errors later on. Getting swamped by bazillion DRC errors “which are OK” as they are within BGA breakout region has a potential to miss other DRC violations which might actually be a problem, so turning DRC off board-wide is not really a solution. I’m sure I’m not the first one who need controlled-impedance traces in my design, so I wonder how other designers solve this problem.
I will say that I’m migrating into Kicad from other CAD package, and there you can assign a netclass to the part of the track, so I would mark breakout part of tracks which less strict netclass and thus eliminate DRC errors while still having DRC checks on the rest of the track.
Thanks for any hints/suggestions.