Controlled-impedance traces tend to be pretty wide - in my case based on a stack up provided by my fab, they need to be 0.295 mm with at least 1:1 clearance. So what I did is defined a dedicated “Highspeed” net class with 0.295/0.295 trace width/clearance. However in BGA breakout area where is not enough space between pins to have such large tracks with this clearance, so thinner traces need to be used (and it’s OK and recommended technique by chip manufacturers).
In Kicad pcbnew, I can make traces thinner for a part of it’s way, however clearance still comes from the netclass and I couldn’t find a way to change that, consequently pcbnew does not allow me to route traces unless I disable DRC, and I get a ton of errors later on. Getting swamped by bazillion DRC errors “which are OK” as they are within BGA breakout region has a potential to miss other DRC violations which might actually be a problem, so turning DRC off board-wide is not really a solution. I’m sure I’m not the first one who need controlled-impedance traces in my design, so I wonder how other designers solve this problem.
I will say that I’m migrating into Kicad from other CAD package, and there you can assign a netclass to the part of the track, so I would mark breakout part of tracks which less strict netclass and thus eliminate DRC errors while still having DRC checks on the rest of the track.
Thanks for any hints/suggestions.
Only thing that comes to mind is a work-around.
Put in a part in the schematic (2 pin connector) that essentially boils down to a piece of 2 pads connected by copper and have different net classes on either side.
Setting net class clearance is the only practical way to get length matching to work as otherwise I’d have to manually check each and every “wiggle” to make sure it doesn’t come too close to another trace. This would be kind of OK if you have only few highspeed traces, but when it comes to massive parallel buses like DDR3 - it will be a nightmare.
Also these seem to be a bug in OpenGL canvas which always enforces DRC regardless if “Disable DRC” button is pressed or not. Which forces me to switch between “default” and OpenGL canvas all the time - trace length matching only works in OGL mode (but not in default), while “disable DRC” button only works in default mode, but not in OGL. Side question - is there a reason for such discrepancies? It feels very odd to me as a newcomer into the package.
I thought of something like that, but that wouldn’t work because controlled-impedance traces in most cases are on internal layers, and bringing them out in the open would destroy signal integrity (by creating stubs and impedance discontinuities along the length of a trace - this is a reason most chip manufacturers strongly advise against layer-hopping of high-speed signals outside of breakout regions). Which is the reason CI traces are used in the first place.
With PCBnew in Legacy Canvas mode this works - somewhat. Pad isn’t visible by itself, but can be used (put tracks to it).
Would need some visible guide on another layer to ‘see’ it visually.
Saving and reloading PCBnew doesn’t like it though - crashes.
There is no problem having controlled impedance traces on outer layers. Of course any high frequency signal, controlled impedance or not, will tend to increase EMI but that’s a whole different ball game.
Of course it’s a good idea to keep layer changes to a minimum but impossible to completely eliminate them. Stubs can be avoided by using blind/buried vias.
You’re not providing enough information (ie. stackup, prepreg thickness etc) It would seem, based on your trace width/spacing of 0.295mm (11.6mils) that even though you’re routing your signals on an inner layer you only have one reference plane making it a microstrip. If this is the case then one solution would be to add another reference plane making it a stripline and halving your trace width/spacing. Inner layer traces would then be 0.148mm (5.8mils) and outer layer traces would be 0.295mm (11.6mils).
Unfortunately KiCad doesn’t allow netclasses to have different rules for inner/outer layers. You can however, switch between netclass and custom width for a track while routing in the OpenGL canvas.
I’m planning to use 4 layer board with 1.2 mm 1oz (0.035 mm) base and 0.175mm prepreg, CI traces are on a bottom internal layer (In2 in kicad) referenced to the bottom outer ground layer - this is my personal hobby project so going to 6-layer board would increase PCB manufacturing cost more than twofold.
Too bad it only allows custom widths for a track and not custom width AND custom clearance, which would make more sense to me. I will take a look at the source code to see if it can be hacked in (I’m professional software developer so that shouldn’t be too hard).
DDR3 on a 4 layer board, I assume with only 2 signal layers? I wish you luck.
I don’t know where you get your boards made but going from 4 to 6 layers is usually a 40% to 50% cost increase (depending on board size). That’s for as few as 5 boards, it’s even less for 10 or more. For 8 layers you’ld be looking at double the price.
No, current board have a pair of Cypress HyperRAM modules running at 166 MHz DDR (so effectively 333 Mt/s). I mentioned DDR3 as example of the case where you need to have set up proper clearances just because there are too many traces to look after manually.
I order my boards at allpcb.com, the basic 4 layer board is just under 35$ for 5 boards of 100x100mm, while 6 layer board with same specs is almost $150. As you can see there’s a huge difference, especially since I pay for it out of my own pocket.
Yes, $35 for 5 is typical for budget 4 layer PCBs out of China. You’ll notice however, as soon as you specify controlled impedance the price shoots to over $100.
Correct, but then $223 is not a very good price for 5 6 layer boards. 50 boards are virtually the same price.
According to their website,
5 4 layer boards with CI = $81 (an hour ago this was $108)
100 4 layer boards with CI = $102
5 6 layer boards with CI = $223
100 6 layer boards with CI = $227
5 8 layer boards with CI = $293
100 8 layer boards with CI = $297
They do have a disproportionate increase from 4 layer to 6 layer, while 6 to 8 layer is a more reasonable 31%. There’s also virtually no difference between prototype and production quantities above 4 layers (it’s mostly tooling costs). But these prices are for 6 mil track/space and 0.3 mm hole, reduce them and the 4 layer board quickly gets more expensive.
Not the best prototype pricing I’ve seen but if you can route your board with 6 mil track/space and 0.3 via holes on 4 layers then you’re all set. Although I would order 25 boards for the same cost.
I think it’s the other way around - they’ve optimized their manufacturing for 2 and 4 layer boards, so that they can make them extremely cheap ($5 for 10 two-layer boards up to 100x100 mm is VERY cheap), while more complex 6+ layer board’s cost is more in line with competition.
This is even more evident if you take a look at “made in USA/Europe” PCBs - 2 and 4 layer boards are many many times more expensive than Chinese fabs, but as you get into more complex boards, the price difference becomes not that insane anymore.
If you know a fab with better pricing (but still good quality) I would appreciate if you’d share this info. I do a lot of boards as hobby projects, and can never get them right on a first try without several re-spins , so any savings will mean more (or better) chips on those boards!
$10 for 200 is even cheaper, $13 for 500 cheaper still. Why would you only order 10??
I’m not sure I trust those prices.
I usually either get boards made locally here in Australia or, if time permits, I deal directly with the Chinese fab. I don’t usually order less than 25 boards.
Maybe because I don’t need 500? And I only have so much room in my home for that stuff? Pick the one you like Most of this boards I only really need in just a singular quantity, I order 5 or 10 just in case I mess it up somehow. If I could order 2-3 (especially as move onto more expensive boards) I definitely would.
I do. Ordered many times there and in another Chinese shop - pcbway.com. They are very fast (7-8 days from order submission to holding boards in hands) and I’ve never had a defective board from them (they do flying probe test, and you can even see marks on pad’s HASL from that probe under microscope).
In response to the original question, I have routed a 484 pin BGA with 600Mbps LVDS pairs (300MHz Clock, DDR) in KiCAD and it did take jumping through some hoops. In my case, these were LVDS bus pairs, so a set of eight pairs needed to be routed deferentially with controlled impedance and length matched. Here is what I did:
Create a Netclass for the LVDS Bus nets
Set the Netclass DRC rules for my BGA escape routing
Route all nets from the BGA pads to the edge of the IC
Check DRC of the escape routing
Change the Netclass DRC rules for board run routing
Complete the differential routing and tune lengths (outside the BGA area)
Check DRC of the routing outside the BGA area (note you will have a lot of red arrows under the BGA)
This was on an 8 Layer board with the LVDS buses on an internal layer.
No problem. Someday having zone-based DRC would be nice to have, but I there are a lot of more important features to tackle in KiCAD for the moment. When I first routed this board, the differential routing wasn’t even the the DRC rules yet, so things have already come a long way fairly quickly.
Although I would order 25 boards for the same cost.
, so any savings will mean more (or better) chips on those boards!