key strategies to minimize interference and ensure that the PCB operates reliably?
how to do read parameters from the simulation results is it a way or possible guide maybe if I can get information on what to reduce and what not to maybe some AI thing ?
carefullyā¦
This isnāt really KiCAD specific thoughā¦
The first key strategy is to have a single GND plane.
The second key strategy is to have two complete GND planes.
Two GND planes would be very good, on a dual sided PCB, and as it does not leave any room to route signals or even power to ICās. you will not have any EMC problems. A minor inconvenience is that your circuit also will not work at all. Two GND planes on a dual sided PCB is not practical.
For 4 or more layers, two GND planes are both practical and advisable. The reason is that prepreg is much thinner then the PCB core, and the closer the GND plane is to the (high speed) signals, the better the coupling is for the return current, and better coupling is less stray EMC (both receive and emit).
Rick Hartley (from altium) has posted an excellent 2 hour and 19 minute video about creating a proper ground plane. The video is both interesting and important enough to watch at least twice (with a few months in between). Have pen and paper or a text editor ready to make some notes.
All off-board connections are also of primary concern. Every wire or cable connected to the PCB is an antenna and filtering components are common. From inductors in power lines to ferrite beads and feed through capacitors.
Another common practice is the configurable output drive of some microcontrollers and other programmable stuff such as FPGAās. The faster the flanks of uC pins, the more EMC they will create. Series resistors can be used to decouple an output pin from the track capacitance. Thinner PCB tracks result in less capacitance, and thus less peak current and less EMC problems. I once built a uC circuit on Matrix (vero) board. It was continuously scanning a keyboard matrix, and I also wanted to use the built in ADC. That was a big mess, but also an educational moment. If you can build your uC circuit (first prototype) on a matrix board in such a way that it behaves reasonably nice, then it probably behaves excellently once a real PCB with a decent GND plane is made.
Look into near field probes. These are often very expensive from the āwestā side of this mudball we live on, but there is not much in them and a cheap set probably works (almost) as well. You can also DIY it, but you probably need a pre-amlifier as they do not deliver much output signal.
With simulators you can identify locations of quick current changes (which are a mayor EMI source), but a SPICE like emulator is not of much use for EMC. You can characterize cable filters with it, but PCB layout is an extremely important part of EMC performance, and to do that you will need an electromagnetic field simulator, and that is a completely different beast. This tends to be more specialized (expensive, little Open Source available), but even watching some youtube videoās help to build insight in how electromagnetic fields around wires behave. And you can use that insight to improve your PCBās even without having used such an emulator yourself.
Ground rule is that electrons move through conductors, but nearly all the electromagnetic field (and thus energy) is outside of the conductor. Shaping the form of that field (with GND planes, shielding) and itās rate of change (fast output pins, chokes, inductors, resistors, etc) are the mayor ingredients of the game.
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thanks! specially for mentioning the video ! I will watch that
There are also lots of other good videoās (and books and complete courses) covering the topic of EMC. Robert Feranec comes to mind. He talks a bit slow, but the content he produces is solid.
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Whenever such kind question is asked I remind links to articles I found around 2004 and have given here at forum in 2020:
Circuit simulation is useless for EMC compliance. Only the, very expensive, field solvers are helpful.
Most of us donāt have these tools, so just depend on a good ground plane - avoid the star point theories, and using decoupling as close as possible to each power pin. For SMPS, think where the current flow loops are and minimize them.
I donāt agree with this sentence.
Nearly 100% of my PSpice use was related to EMC.
I have designed ESD gun model, Burst and Surge generator models. Then I connected them to my circuit input and output protections to see what will happen. Resistance to these pulses is part of EMC compliance.
I analyse each my device supply filter (using all elements with their parasitic components) to see if frequencies generated in my circuit are well filtered. I also analyze DCDC output filters to see how much of DCDC noise I have at VCC as it then is emitted by VCC supplied transmission line driver. Conducted emission is also part of EMC.
So, not for all, but at least for some EMC aspects circuit simulation is helpful.
I also disagree with it. Its extremely complex for sure and takes alot of back-annotation from layout BUT it is possibleā¦I have reasonable good correlation of my emi simulations with regards to my high power inverters but this is simpler than other electronicsā¦
A bad layout, where traces and different planes overlap introducing stray capacitance, will make such simulations more involved but also will cause emi issues themselvesā¦
At least you can see in a simulation how quick voltages and currents are changing, and these are the main creators of EMI. This is logical, but it is very often disregarded. Do a quick search for SMPS and āhot loopā for example. It explains why the inductor is not a big part of EMI problems. The switching is taking place between the input and output capacitors, and in between them are the (MOSfet) switch and diode (Assuming standard buck converter).
In how much EMI this will result, a ngSpice simulation can not tell you, that is mostly determined by PCB layout.
But you can also use a simulator for modelling all cables as antennaās and then get some idea of the effectiveness of ferrite beads and other filtering parts.
It would be nice if you can share some of this with the big ngSpice examples thread, which is now mostly maintained by Holger. 
Examples for this are particularly relevant because the circuit to simulate is simple, and because it also is relevant in any PCB.
There is a problem.
In 90s Iāve got PSpice demo version (limited to 30 nets, I think).
These models I have done 20 years ago (2002-2004 I was preparing to we join EU with CE and EMC). I did some simulations till 2010 and later I didnāt need them. Last time I could run PSpice was in 2017 at Windows XP. In 2017 together with moving to KiCad I moved to Win7 64 bit and since then my PSpice donāt wants to work.
Of course you could stand on your head and run it but I have never run a virtual system on other system. Donāt know how to start it and if I will be successful. I have no practical need to see any of my PSpice circuits and no time to play with it.
In PSpice I had a symbol like PWR_FLAG in KiCad where you could write a start voltage for the net you connected that symbol to. My pulse generator models were based on using it.
If remember well Surge is 50us voltage drop to 50% and 8us ? current drop to 50% (if output shorted internal capacitance lost charge faster).
When connecting not to power pins but to signal lines the 40Ī© resistor is used in serie with it. When such output is shorted by transil you get 25A from 1kV pulse but even it is current pulse it is longer as true generator is shorted by 40Ī© and not by 0Ī©. This current pulse drops to 50% in about 47us, I think. So I use 25A 50us pulse as my reference what my inputs have to withstand.
It was so obvious for me that once at IEEE: EMC-PSTC mailing list I just said about 25A 50us pulse and was asked from where I have it as no standard specifies such pulse.
If you add estimates of the parasitic inductances and capacitance like this, simulation starts becoming much more realistic. Not trivial and the part I struggle with is estimating magnetic coupling between traces.
I agree, the magnetic coupling part is ā¦ borderline āimpossibleā. This is the exact situation I am in with a 1000A inverter I am designing and thus have powercore simulations for EMI reasonsā¦ I am confident in my L and C stray (either datasheets, whitepapers, measurement, experience)ā¦ HOWEVERā¦ there is coupling from the large fields to chassis that will shunt past the CM inductance, CM inductance that is added for EMC reasons.
A SVPWM excited 3phase inverter, with key parasitics takes about 20h to simulate 6ms: Permitting to go to low enough timestep to realise the dynamic switching behaviour of the switches with enough fidelity to reconstruct at 100MHz while also have enough cycles to reconstruct downto 150kHz ā¦
At PCB levelā¦ its slightly easier, especially if āgolden rulesā with regards to layout are observed such that the h-field coupling is beneficial not detrimental
Regarding, " How do you design for EMI/EMC compliance?"
There is no substitute for understanding and it take some effort of the several phenomena to be covered.
Some generalities.
Learn how to design antennas and do not design systems that are antennas.
Learn how to make transmitters and do not build transmitters into your design.
Every single signal (net) should have no greater bandwidth than is necessary for itās function. This generally means as much series resistance as is compatible with normal operation.
Design how currents flow in every circuit and minimize cross sectional area (which is a magnetic induction into other circuits which become antennas).
Most of how you need to think is about current circulates and that is not natural for many who think in terms of voltages.
A lot of the advise above about ground planes is correct and the reason can be understood by the way I wrote above about minimizing the cross sectional area of current loops.
Finally I ask other readers here if there are some good Youtubes where some one demonstrates how to design BAD EMI and then correct it? Neary 30 years ago I have seen a live seminar which demonstrated bad and then good.
Some more specific advise.
Power supplies are where many signals mix which is undesirable and so it is where we must start.
EVERY load (an integrated circuit for example) must be ādecoupledā and āBypassedā from the raw power supply distribution. You ādecoupleā with the maximum series resistance compatible with normal operation. Sometimes you must also use ferrite beads for additional series decoupling. Local to every load must be capacitors, by pass capacitors, which provide the high frequency currents for the load. High frequency currents must NOT be expected to come through the raw power traces because such traces are long and are therefore better antennas.
Every signal must have a series resistor near its source to limit the bandwidth on traces (limit rise and fall times) and for some cases you even add discrete capacitors to slow rise times.
When 20+ years ago I was searching for EMC information I found this:
I specially liked his āTidbitsā (one of them was even caused by my email send to him).
I later noticed that he begun to make videos but I have enough big problem with understanding speaking English to not watch them. But since he makes his living as an EMC consultant, I believe theyāre on topic and interesting.
I found this 4 part series recently and like it, short videos clearly explained.
Thanks for the link.
I have a NANOVNA and the articles I see here give me ideas for some measurements I hope to make time for.
Printed Wiring Board Coupling to a Nearby Metal Plane is of interest.
Some years ago by making some order of magnatude assumptions and approximating distributed elements as lumped elements I convinced my self that resonance with an enclosure to a PCB copper plane was non negligible by the time you get to a few 100s of MHz.
I conclude that solid power planes are likely not a good idea.
I have designed boards with solid ground planes, installed in metal enclosures for military products.Bonding the PCB around its perimeter to the case, at intervals that are not too large, becomes important to avoid creating a patch antenna. In a commercial plastic enclosure you donāt stand a chance without a ground plane
Around 2002 I spend some time just searching internet for EMC and among many others I found articles I mentioned at the beginning of this thread and this page.
These are the best what I found but I think that nowadays there are probably much more EMC information in net so may be the best way for you would be to just search them.
Most my PCBs are 2 layers so I have no problem of planes working as waveguide and resonate.
I think that when you have planes at several layers it is good to end each in different place and to avoid rectangle shape of whole plane so to wave will not go forth and back resonating.