I am not sure what the problem could be, it is working in my v9.0.3:
1mm
5mm
Just thought I’d ask, just in case . . . you aren’t talking about this text are you ?
Yes, that’s what the DRC is flagging. And I tried changing the min height o 3mm and I got a change on the other text, but this small text was unchanged.
It seems to appear when any of these layers are visible:
I’m using the defaults that came with the software:
I don’t understand why SOME text is not following the rules. Most of my designations look right, but there are these “ghost” items that are too small to see, but cause the DRC errors.
This only happens when I use a schematic imported from LTspice, updated in the Schematic Editor and then F8 transferred to the PCB Editor.
Nope, that just the netlist label, I’m pretty sure you cant change it’s size, DRC will not be complaining about that text, 100% guaranteed.
If you run the DRC again, find the arrow you are concerned about, zoom in and click the arrow the corresponding Error will be shown in the DRC list . . .
Nope, in that image it is actually the Silkscreen J5 text that is smaller than your constraint.
The 1 in that image is simply the Pin Number . . .
After this step you need to re-apply the defaults so they go back to the min 1mm height specified in your defaults . . .
If you go to Edit > Edit Text and Graphic properties . . .
Then set what you want to change, Reference designators for example, and select the radio button next to Set to layer default values then click Apply (bottom right)
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So the very tiny text is net lists. I think then that the J5 designation triggers the error because it’s in a drillout area. I didn’t need two J5 silkscreens, so I deleted all the duplicates. That cleans up a lot of the errors.
What remains is working out the clearance violations. I’ve right-clicked and chose to exclude some devices, like the small transistors, since their pads are closer together. Hopefully they will stay out of the error list from now on.
I’m very close to a completed PCB now… just have this recurring clearance violation for the two small transistors.
There’s probably a way to make exceptions for them, but in the DRC, if I right click and make exception, it returns the next time I run DRC.
Is there a way to properly exclude Q1/Q2 from the general clearance rules?
I’ve tried this:
But still get the error:
Am I adding the override in the wrong place?
Another option is to move the pads a bit further from each other, or simply use the TO-92_Wide footprint.
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I use this footprint and don’t get this error. I looked at the footprint and indeed the clearance is 0.2268. So I think the library footprint has a clearance override and the third message suggests that you have mucked with the copy in your layout such that the board clearance applies. Maybe you should Update footprint from library?
Although TBH, I have found soldering this footprint by hand a bit finicky and a little prone to solder bridges. So these days I sometimes use the wider or the inline version.
Although it’s off topic from the title and original question, the various exchanges taking place here are topics that are widely experienced by everyone, so if the official documentation were updated with some experiences, it might help everyone learn how to use it.
I find this thread a bit tedious and did not read it all, but very likely nearly everything here is already mentioned in the manuals, and in various tutorials too. It’s pretty basic KiCad beginner stuff.
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None of the official volunteers have time for this sort of thing. That’s what search engines are for. Though TBH the Discourse one isn’t great. If you are keen enough to volunteer, you could put together and submit FAQs. Some have already been contributed for common issues, like personal libraries.
Plus, it’s hard enough to get some newbies to read the official documentation and resist the urge to dive in, or rely on experiences with other, different EDA suites.
When building something for the first time, sharing “mistakes in thinking” and the “correct solutions” to them as personal experiences rather than as a reference manual will increase the chances that beginners will notice the same mistakes.
The two biggest problems to overcome in this thread were: the importing of a LTSpice circuit for the schematic and the use of freecad to draw the PCB. I guess using these was supposed to save time and effort.
Judging by the time of, and length of, this thread, I doubt using either saved anything.
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“I know a shortcut to a shortcut.”
(Later)
“Well that turned out to be a longcut.”
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At least this thread is mostly about using KiCad . . . and yes it’s mostly covered in the Documentation/FAQs, but sometime we all find it hard to see the wood for the trees.
I’m happy to help where I can especially if it gets this User away from the Autorouter 
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I only mucked with a relay footprint on the first PCB I made in June. Did not modify any of these transistor footprints as they already came with the device type I selected.
Also, was not aware there is a wide version of this footprint. I had assumed I get what I get when I chose 2N2222 as the device. It’s good to know there are alternatives.
I can ignore the clearance violation, as long as the PCB fabricator doesn’t choke on it.