Thank you for reply. Why do you think that is a better layout? All the high frequency currents are running through the ground plane. Your ground plane is not good ground anymore. Please correct me, if wrong 
Thanks
Afaik (might be 100% false) the XTAL lines are connected to the IC generator, there is no current running through the ground plane, they are isolated.
And as long as you donât use a 200kHz SPI bus there or even faster stuff I wouldnât worry too much about the issue anyway.
What is the clock for the IR PWM?
There is nothing lower impedance than a ground plane. Using tracks for ground inevitably means that the cpu I/O is noisy relative to ground and sprays RF everywhere.
These days EMC design consensus is to have a single ground plane and avoid multiple grounds with a star point
1 Like
He could include a second plane as he did originally.
This way the current does not go through vias.
I think infineon and stm suggest to do it this way.
Your placement of the Capacitors is still better in this case. (C5 originally would have had a very long way for its current to reach a ground pin.)
The frequency of Y1 (clock) is 16MHz. The IR PWM (pin SS) frequency is 36kHz. Are the traces from mcu (pin SS) to mosfet to long in my case? Should I use the bottom layer to make the IR PWM (from SS pin) trace shorter or should I leave it on top so I donât have a trace on main GND plane? Which is better?
Also the question about the crystal layout. Based on your responses I made two layouts (two options). The first one is with the local ground plane on the top. Which option is better?
OPTION 1:
For option 1:
You should connect pin 5 to the top ground plane. Makes the return path for C4 and C5 a lot shorter.
You are correct, I somehow missed that. Thanks. What about the trace from the SS pin? (look at the picture in my upper post, also posted today)
Low speed I/O tracks can be fairly long without problems, provided the the CPU GND and Vcc are going to be clean as they are basically attached to one of these. Now you have good GND connection to a plain and the Vcc is well decoupled, you should be OK.
Great, thank you all. I guess everything below 1 Mhz is considered low frequency?
Not quite, rise and fall time come into it. Series resistors or ferrite beads are used to limit these.
What matters a lot is the position of external connectors. All on one side of the board is good, which is why switched mode power supplies are made like that. Cables on opposite sides is the worst as you are making a dipole antenna driven by any noise across the board.
1 Like
You have many unnecessary vias and tracks in your ground plane. C1 is virtually useless. Your local ground plane should have several vias stitching it to the main ground plane. The oscillator layout is improved but thereâs room for more still. And thatâs just on the part of the board we can see in the pics above.
You could clean the layout up a bit by rotating R1 180 degrees, run the âSSâ track outside J1, remove the vias and track under U2. For a start.
1 Like
@davidsrsb I understand what you have written. If the mcu produces a 36kHz pwm, that means that the signal contains higher components (the sharper the edge, the higher the frequency components). Am I correct? But that means it depends on the mcu how good the pwm signal will be and what higher frequency components it contains. Am I correct?
@1.21Gigawatts
I have rotated the R1, thanks. Why should âSSâ track be outside the J1 and not beneath it? (J1 is a switch). I also cleaned up that unnecessary via and track under U2. Why do you think C1 is useless? Isnât that a standart practise that you put a decoupling capacitor at every side of MCU where Vcc pin is? Now I have two capacitors, one at each side.
Run the âSSâ track around the outside of J1 so you donât need to jump it with vias and a track in the ground plane.
As for C1, see this post:
Complex ICs with a lot of I/O often have separate power pins on each side to reduce ground bounce. Often the Vcc pins are not even internally connected. One 100nF ceramic on each side with a Vcc pin is good practice. I donât bother with a Vcc plane until I have 6 or more layers
1 Like
@1.21Gigawatts I read it and I understand the difference between decoupling and bypassing. But I still donât get it what is the reason for not using C1. Is it because of the position of the power supply, which is on the top right, so only a capacitor on the right (C6) can do its job (return path for high frequency signals)? I posted a photo below.
I also changed my traces a little bit, the ground plane is now even cleaner.
C6 is okay, other than being compromised by having to decouple pins 4 & 6 as well. It would be much better to provide a more direct connection to 5V for pins 4 & 6 of U2. You could route a track from the pins 6&7 of U1 up and around D1,D2 to supply pins 4&6 of U2. Ideally both pins should have their own decoupling capacitor. Donât worry about reducing the size of the local ground plane. Zones donât have to be rectangular, you can be a little more creative. 
Yes, much better. While itâs not extremely important for this particular board itâs always good practice to reduce unnecessary vias as well as maintaining the integrity of your planes. There is one more âjumpâ you could eliminate by moving the â9Vâ track. Also, remove any tracks that make ground connections, such as the track between C2 & C3. Instead use a short track and a via to connect directly to the ground plane. It also wouldnât hurt to make your 5V tracks wider if you have room.
Thanks for great suggestions. I did all, I just didnât figure out how to avoid the â9Vâ track, but itâs a short one, so I think itâs not a big deal⌠You can see the changes in the photo below. I modified the local plane, but I am not 100% sure if I could reduced it more.
So as I understand you are saying that ideally every power pin of a chip should have their own decoupling capacitor. But in the last post, you said that C1 is useless. I donât understand (I am very interested in this topic and looking forward to your answer). Thanks!
C1 was useless, or at least less effective, before as it had no direct connection to your supply voltage (5V). You have corrected that now. And yes, every power pin should have itâs own decoupling cap if possible.
That 9V track could go down the left side of pin 2 of the LED, but itâs not important. But you should remove the 5V track that crosses under U2.
1 Like