After I accept it says DRC error: this start point is inside or too close
an other layer.
Jordi Altayó
Ok i think we will need a bit more information there.
Can you post a screenshot of the board before you add the zone and one of the error message?
(Maybe make two posts in this topic. Because new users can only post one picture per post.)
This is my layout. I want to fill the space under the IC (U1 U3) because I make my boards using a CNC. And if those areas are empty it takes a lot of time (i dont have the appropiate tool for big areas). After my board is made I plan to remove manually those areas.
I would create a zone with approximately this outline:
And give it a higher priority than the ground zone.
Repeat the same under U1 and U5 and it should be done.
By the way if you move c12 towards left you should be able to connect it to gnd. (put the two traces that are in the way at the moment between its pads like you did with c2.)
Also you want this capacitors to have a short distance between the + and gnd pin of the ic to which they are connected. (they generate the short signal return path for switching currents inside of the ic.)
how to select no net?
Hi,
this question means you have not even try to create a new “no net” zone. Please, help anyone trying to help you.
Rene_Poschl has shown you the first choice is the option.
After I accept it says DRC error: this start point is inside or too close
an other layer.
You can make a zone inside or overlapping another zone. Just give the zones different priority levels. Zone settins, 3rd column.
Regards,
Pedro.
I was bored. Ok i’m lying i should do something boring instead of this 
Here more details on why the capacitors connection to the gnd and vdd pin matter.
(Very simplified. The exact shape of the current path depends on a lot of things. But as a first approximation this should be ok.)
The datasheet tells you only to keep the connection to vdd short because they assume you have a ground plane on another layer. This way the gnd connection would always be the shortest possible.
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There is a screenshot of the error I get. If you whats closely you can see the pointer where I tried to start the Fill Zone.
I don’t know how to set the priority of the layer
I played around a bit.
You don’t need to set the priority at all. (Or at least in my kicad version i don’t need to.)
I copied my test zone (selected it with a left-click. After that i duplicated it via crtl+d. And placed the copy at the same space as the original zone.)
After that i edited one of the zones properties and selected no net.
If this does not work. Can you give us your kicad version. And the operating system you are using?
But because you might need it later on anyways: Here the info on how to set the priority level. Higher numbers mean higher priority.
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I had withdrawn that post , it takes 24 hrs to get deleted. I got the no net thing and even implemented soon. Thanks for your concern anyway.
I’m very sorry arvimg. I thought I was answering the one who asked the question the first time. I thought he was asking for help and then didn’t pay attention.
So my apologies for both of you.
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Thanks, it works now!
Instead of adding isolated zones you could easily just move a few tracks and get your ground plane to flood significantly more of the unflooded areas.
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It actually doesn’t have anything to do with the gnd pin and no assumptions are made about a ground plane, the same rules apply for double sided boards.
Sorry to bud in but there is a lot of misunderstanding surrounding decoupling capacitors and while I’m no expert I thought I would try to help clarify a few things.
Decoupling capacitors are also sometimes called bypass capacitors, they are in fact both and as such they have two jobs to perform.
Decoupling:
Datasheets always state that the placement of the decoupling capacitor should be as close as possible to the Vdd/Vcc (pwr) pin because that is the pin that needs to be decoupled. Consider an output of a high speed bus driver. When that output switches from a low state to a high state it has to source enough current to drive not only the load but the parasitic capacitance and inductance, aka impedance, of the PCB track. This transition takes place in only a few nanoseconds, the rise time, causing a large current demand at the pwr pin. The regulator supplying current to this pin is unable to respond quickly enough to supply the required current, not to mention the impedance of the PCB tracks/planes (PDN) that need to deliver this current to the pwr pin. The result would be a voltage drop at the pwr pin the severity of which would depend on how many outputs toggled simultaneously. This is where the decoupling capacitor comes in. The pwr pin does not connect directly to the power rail but rather to the decoupling capacitor and the capacitor connects to the power rail. During the transient state the capacitor supplies the current to the pwr pin preventing the voltage from dropping. By doing so it effectively decouples the pwr pin from the power rail.
Bypass:
As has been mentioned elsewhere when referring to return paths, the current sourced by the above mentioned bus driver output will take the path of least impedance to ground. For low frequency signals this would be ground at the load as one would expect. High frequency signals however, will return to ground at the “source” of the signal and the route taken will be adjacent to the track carrying the signal where ever possible. This might be a ground plane on the adjacent layer, it might be the power plane on the adjacent layer. In the case of the latter the return signal arrives at the power pin of the bus driver and travels through the bus driver to ground. This is another unwelcome situation. Fortunately the decoupling capacitor that we already have in place provides a low impedance path to ground allowing the current to bypass the bus driver IC.
Hope this helps.
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Very good explanation. But i’m a bit unsure about your statement that the connection to the gnd pin is unimportant. (Or have i interpreted something wrong? I think you have more experience than i have.)
As far as i understand it the connection of the decoupling/bypass capacitor to the gnd pin is at least as important as the connection to the vdd pin.
Especially for fast switching cmos devices (a micro controller typically is such a device).
They create a low impedance between their internal gnd and internal vdd while switching. (Both the n-channel and p-channel transistors are on for a short time.) This current is on top of everything you mentioned above.
What happens if the gnd pin of your ic is not connected to the same ground as your decoupling capacitor? (C2 of the original image.)
What happens if this connection is very long?
I think the problem in this case is that at least part of this current will take a route which is undesirable. (Either very long => antenna, Or it uses another pin and couples via some stray capacitance back to the decoupling capacitor.)
To avoid problems some ic manufacturers build ics with gnd and vdd pins close to each other. (The arrangement used by most logic ics is not ideal from an emc perspective.)
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Sorry, I didn’t mean to imply that the ground pin is unimportant, it of course sinks similar currents for the opposite transitions. But it has no influence what so ever over the placement of the decoupling capacitor. There is no regulator or any other active device supplying current to the ground rail (most of the time) so there is no need to decouple the ground pin in a similar manner. Nor is there any reason to bypass it. When it comes to ground all we can do is provide the lowest possible impedance back to the power supply. Decoupling caps must be located as close as possible to the pwr pin so the trace between the pwr pin and cap is as short as possible to minimize inductance and allow the cap to do it’s job.
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Decoupling Caps :
Let me put this in simple terms.
Capacitors block DC and pass AC (frequency depending on RC values etc).
So :
A Coupling capacitor is used to link 2 circuits’ SIGNALS. DC is blocked and AC can pass.
A Decoupling capacitor is the opposite, attempting to block the AC signals to provide a more stable DC power.
This is because AC ripples can be induced in the wiring via interference, power supply ripple and circuit RLC parasitics resulting in the overpowering of your IC pins when it adds to the DC component or the complete breakdown of your timing circuits.
The reason we decouple even in frequencies of less than 2GHz (where parasitics are actually prevelant and S-parameters come into play) is because of the tiny distances between conductive elements and components on the board and magnetics over which we have no control. Currents WILL be induced.
(Often the internal circuit of the IC is designed with requirement of this external capacitor which is essentially treatable as part of the internal circuit and can not be foregone. You can usually check this in the datasheet where they will show you the internal circuit).
The length of the path of a GND route is of equal importance really, to the power route, provided the GND is a thin trace. If the component can be immediately connected to a wider GND plane this will serve to reduce impedance.
I will re-iterate that Power Supply Ripple is a major factor as mains power is a very dirty signal. People starting their cars in the street will cause plenty of interference in your mains wiring because of the mass and length of the copper in your house, alone. Unless you have a super expensive and over engineered power supply this ripple will propagate through your circuit.
[Galvanic coupling, I do believe, actually occurs between 2 dissimilar metals in the presence of an electrolyte. Not the same thing as ‘ground bounce’ which occurs from the resistance of the conductor between the component and the ‘true ground’ point causing a drop in voltages across it, leading to ‘residual current’ effects and possibly electric shocks and broken components… the very reason why we install our home power in a ‘Ring’… to halve the resistance of the Local Ground before the power reaches the True Ground point].
