Exposed copper pour / fill zones? (pour with no solder mask)

Oh… uh…
You want the ‘intelligent’ poured area - and only those - to be without solder mask… :scream:
I have no idea how to do that, sorry.

I mean, I would have an idea how I would personally try this (manually editing the kicad_pcb file, shortly before creating the gerbers and no further changes are expected), but I wouldn’t suggest that, unless you’re really desperate.


Do you have any guide/info on how much better you are without soldermask?

I was imagining some bigger areas to be soldermask free, and having smaller ‘islands’ covered by it… but as we don’t know how the ground plane looks like it’s hard to say.

No worries thanks @Joan_Sparky

no, but most be better performance surely?


A ‘little’ yeah, but the problematic interface is ‘material’ <-> ‘air’ anyway. The soldermask is really thin, it won’t really matter, unless you already did all you could and need 1 or 2 deg K per W more for some very special edge case?

Just read up on convection and heat transfer from materials to air… surface area counts, turbulence in the flowing medium counts, etc… but material properties (especially for thin coatings) will have no influence really (as heat transfer resistance over such short distances doesn’t really differ between metal and coatings).
If you wanted you could mount some heatsink onto that copper area, that might help a bit. But as I said, no idea if useful, as we don’t know what you’re doing :wink:

interesting info @Joan_Sparky

wasn’t planning to add any other heatsinks to the copper, but just use the copper layer as a heatsink as much as possible.

I agree with Joan. The thermal conductivity of copper, and the thermal capacity of copper, is high. For example, copper bottom cooking pans take a long time to heat up because their capacity for heat is so high. And they are uniformly hot across the bottom of the pan. Air layers are thermal insulators, but not paint. And the dark solder mask is a good color for radiating heat.

Also, what’s wrong with a bare board (generating a zone that omits the solder mask over the entire board?) You would still have bare PCB between copper traces to prevent solder from bridging between traces. Solder mask is often optional, unless you are doing wave or reflow soldering.

Interesting points

yes worried about solder bridges, but perhaps Im being too cautious … Im am doing reflow soldering though

I apologize for bumping this topic up again, as it is rather old, but I was wondering if anyone had solved this problem? A lot of SMT parts now have an “exposed pad”, sometimes called a “paddle” that is used for heat transfer. Typically this is “stitched” full of vias to improve thermal conductivity. Occasionally a polymer heat-transfer “gap pad” is used to carry heat from the back Cu to a heatsink or the case. In Altium and other programs the solder mask can be omitted from this area. I have been able to draw lines on the back solder mask where I want the mask to be omitted, but they are just lines, not a zone. Trying to draw a filled zone brings up the message that this is only allowed on Cu layers.
Omitting the entire solder mask is (IMHO) bad practice, it not only masks during reflow but provides electrical insulation and protection against debris and to some extent corrosion.

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When I want exposed copper, I just draw lines on *.Mask until the copper I want exposed is covered, there isn’t any other way, but honestly it’s not bad or often needed. Am I misunderstanding what you want to accomplish?

Yes, I am contemplating doing it this way as well! I was just hoping there was a better way.

The DPAK footprint I posted at Pad Holes Under SMT for Heat Sinking and other questions shows an example of how I dealt with this problem. The pad definition dialogs for the pads associated with the thermal tab on that package are posted at How to add via holes on a thermal pad of QFN footprint? . You can look at the *.kicad-mod file in a text editor if you need to dissect all the details down to the molecular level. Bring your critiques, questions, and comments back to this thread for discussion.

(Yeah, the DPAK is a medium-power transistor package, rather than an IC with a thermal pad, but the fundamentals of creating their footprints are essentially the same. Trust me. If you think you need an example of a thermal pad under a “real” IC rather than a transistor package, I have a footprint for an LTC4011 around here someplace . . . but I have learned quite a bit since I made that footprint.)


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Very Interesting, thank you. In the end I used lines, setting the line width to be slightly greater than my grid spacing, so the adjacent lines overlapped. This works nicely, and the edges even have a pleasing “filligree” lol. Inspecting it with Gerbview it does seem to have produced the desired effect. But I can see the way of doing it with pads as you describe should work as well. Now I have two ways to get the job done!

Which version is this ?
If you first select the Layer (F.Mask) then Add Filled Zone that works fine as per attached image below. (Zones in F.Mask and B.Mask. as well as zones in F,Cu
(tested in r7066)

What KiCad PCB does not allow, is Menu change of a F.Cu copy, to a F.Mask, or vice versa, tho there seems to be no fundamental database reason for that.
Probably just a menu-simplify decision.

ie I can manually edit .kicad_pcb F.Cu copy, to F.Mask, and it seems quite ok.
I can even manually edit a voided (ie poured) F.Cu shape, to F.Paste, but on doing that, Plot and Save drop the voids within the F.Paste - which I guess is not a surprise.
I like to see where KiCad PCB breaks :wink:

Using the Pad shapes to control mask is probably the preferred way, up to the point you need a larger area, or something more heatsink-related, than part related.
Then, a Zone fill on F.Mask (& even F.Paste if you want too) should work fine ?

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I am using 4.0.4 stable. In the footprint editor I don’t see any zone fill? The pad approach (and the lines) works, but it is limited. Nice thing is it stays with the footprint and doesn’t have to be fixed on the board.
I see now that the zone approach works, but only on pcbnew, and then the zone is apparently fixed?
I appreciate all the suggestions, there are (fortunately) many ways to do this in Kicad, it seems!

Ah, the example I gave was adding zones to the board, which is fine for something large and few.

In what way is it limited?

Perhaps “limited” is not the right word- tedious perhaps. I had to draw 20-30 lines to get the outline I wanted, plus some more to make the left and right edges not be “frilly”. If I want to change it, I’ll have to delete some lines, maybe reset my grid and line width, and then re-draw what I want.
In the end I got exactly what I wanted, once converted to Gerber, it is just a region, all the history of lines etc is left behind.

You can add filled “zones” to footprints, just not through the footprint editor. Try opening the kicad_mod-file in a text editor. They are highly human readable. There is a polygon entity in this form

(fp_poly (pts (xy 3.5 -3.5) (xy 3.5 3.5) (xy -3.5 3.5) (xy -3.5 -3.5)) (layer F.CrtYd) (width 0.2))

You don’t need to specify going back to the first corner, polygons are closed by default. The width value adds a trace of that width around your polygon. Meaning your corners will have a nice radius. You’ll need to keep in mind it also expands the polygon by half the width value.

Copper pours for nets can’t be added this way though. There is no way of relating them to a pin number. You can add polygons to copper layers, but they won’t quite behave. They will interact more in a graphic item way than a copper item way.

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I have the same problem, I think the simplest way to deal with it would be to allow the copy between layers… (for all layers).
And the job is done, and I don’t think this is a feature that hard.
Locking up the copy between layer is a design error IMHO.

Old old old thread…

Copying a filled zone from copper to non-copper layer would be mostly meaningless. Anyway, you don’t say what you should be able to copy.

There are meaningful copies and there are meaningless copies. “Feature that hard” – you probably don’t know anything about KiCad internals, so you can’t tell what’s hard and what’s not. KiCad has been designed to do meaningful things in PCB design. Allowing anything imaginable isn’t meaningful.

I don’t know if graphical polygons existed back when this thread was started, but that is how one would create a rectangular (or any odd shape) hole in the mask layer with the current KiCad. The difference between (and why the two exist separately) a filled zone is intended to be an electrical connection amongst members of an electrical net. A graphical polygon is just that, graphical. It doesn’t know or care about electrical nets (and thus is dangerous to put on electrical layers).

One can easily put a graphical polygon on a mask layer to cut a window of the shape of that polygon out of the mask. When this is done for footprint reasons it is probably best to put this mask-layer polygon as part of the footprint so when the footprint has to be nudged slightly to make room for routing the mask-layer polygon maintains it’s registration with the footprint. Though, when putting the hole in the mask as part of the footprint (especially for thermal pads where there wants to be copper exposed) one just uses a SMT pad with the mask layer turned on.