Some of my designs use high voltage (up to around 500VDC), so obviously clearances become important. I set up a special net class, and enter the appropriate clearance.
Often the clearance specified by IPC-2221B is larger than the pad distance (a 500V 0805 part for example). This is fine with tracks and zones, but I regularly receive DRC errors because pads are too close. I can also not route the pads sometimes.
In the meantime, is there a clever workaround for this? I don’t want to reduce the clearances, or tracks and fills will be too close, but I also don’t want to be deluged with DRC errors I have to manually disregard.
How about a safety copy? You can always go back… Did have some segfaults in the beginning but those where fixed within one or two days. I would not worry too much, especially as in october there will be a feature freeze with solely bug fixing.
It will get better for sure, slowly, but knowing how the development has gone for years, feature freeze doesn’t mean there will be only less and less bugs. New ones will be introduced all the time, and KiCad may crash where it didn’t crash before. It’s also not “solely bug fixing”. New major features are polished and changed, and some small features added (“new feature” vs. “missing feature” is a matter of interpretation, and it’s still unclear to me if the freeze is only for larger features – we will know more in the KiCon 2020).
I don’t want to be negative or pessimistic, but even in the stable series small bug fixes have introduced new bugs. That’s why nightly builds and testing builds exist – the brave ones test them and report bugs. I want to encourage testing, but people have to know what it takes.
I’m also using some high voltage diodes that have pads spaced a little too closely for kicad.
I could select new parts, sure, but I know these work and I’d like to avoid that. It takes up more board space too. But sure, it’s one option for a workaround.
Edit: I also like to be more generous with track and fill spacing than the standards call for, which makes it a bit harder to accommodate pads.
You may be being a bit optimistic here, is 500V your peak working voltage? If so these capacitors are not suitable, good practice puts maximum applied voltage <70% rated voltage and preferably <60% so your capacitors should be 750V or 1000V rated and therefore will be bigger.
The clearances quoted by IPC and others are more safety related than functional and are there for a reason and should be followed even if your design is for purely your own use
No, my peak working voltage is less than that, closer to 300V. I’m just using it to point out that 0805 @ 500V exists. To be clear, I am following IPC, and exceeding it, for traces and fills.
But if the spacing between pads is less than your spacing for traces then it is worse because now you have exposed copper (only air as the insulator) close together at high voltage. I admit that I don’t have much experience with these voltages (only a few HV power supplies for PMTs, spark gaphodoscopes, and NM64 neutron monitors), but the logic of not breaking trace spacing with pads and/or pin spacing seems valid. Yes, I know air is a fairly decent insulator and is one of the few self-healing insulators, but allowing an arc to form across the surface of a PCB can cause carbon trails that will then act like resistors bridging the insulation gap.
Sure, I understand there is a conflict between pad spacing on components and IPC recommendations. I tend to believe the manufacturers though when they make a rating. Also, I’m hoping to use more generous spacing than IPC calls for, so even if the pads are compliant, I’d rather go bigger.
For what it is worth, IPC spacing can be conservative if you use quality materials and clean processes. Much depends on the environment in which the PCB is expected to run. But, it is a good practice to follow it if you can. Fewer hard questions to answer during a design review.
I am very much looking forward to seeing rule-based DRC implemented. It is a must-have feature for me to consider Kicad for my job.
That the capacitor itself is able to withstand 500V, (Which is the only rating that kemet is concerned about) does not mean that clearances for that part are adequate for using it for such voltages. Those norms for clearances a sum of a lot of different things such as adequate isolation for high humidity or certain levels of contamination of old PCB’s.
Cemet’s rating alone may be adequate if the part gets fully potted, or with conformal coating etc, but the voltage rating Cemet gives for it’s parts are for the pars alone and not for meting any sort of norm. Have you ever looked closely at those X2 rated capacitors with so many stamps from different normalization institutes on them that it’s difficult to find the value of the thing?
For a safe design you always have to use the biggest clearance of your conflicting norms as a minimum. In this case it means that your 0805 part does not meet your clearance and is therefore not fit for your application.
That part isn’t suitable for assembly and operating > 300V. The pad to pad distance is 0.75mm and the IPC recommends 0.8mm for uncoated @ sealevel assembly.
The KiCAD pads for 0805 aligns with the IPC and also Kemets recommended distances of 0.9mm separation, which itself is good for 300-500V assembled uncoated.
Thus your specific problem is either in your component selection or aspects of how you setup the constraints.
Now 5.1.x doesn’t have too sophisticated keepout rules (I am hoping v6 is flexible enough) so what I end up doing right now is lots of keepout shapes,to help me not get too close
Fair enough, it’s probably prudent to use a larger part, but if a component is specified to 500V, saying “it’s not suitable for 300V” seems a little weird. There is definitely a conflict between IPC and manufacturer specifications. (They don’t require potting)
As said before:
Kemet only concerns itself with the strength of the isolation between the capacitor plates.
This is logical, as Kemet has know knowledge of how the part is going to be used.
On top of that there are norms such as UL and CE, and certifications for that which are yet again on another level.
If you want to build a product and sell it on the mass market you probably have to conform to all of those standards, Not just the one that suits you best. It’s one of those things that makes product design a headache.
Another example are the voltage and current ratings on switches and relays.
If the contacts of a relay are able to switch 230Vac @ 10A, this is no guarantee whatsoever that it meets isolation specs between the switches and the coil.
The (almost) square blue “Songle” relays from China are particularly bad in this aspect, while the Omron G2 (clones?) have a wide isolation distance between coil and contacts, they even have a labyrinth built in to increase creepage distance.
Its not really weird, not only because of what @paulvdh and I have stated but the difference between working and transient
The IPC typically is concerned with working voltage, the voltage that the circuit is expected to stand off for a considerable length of time. When you consider BSEN-60664, the distance before a flashover occurs for a short duration transient is a lot larger. If a circuit is anticipated to experience an overshoot (be it due to an underdamped 2nd order system, supply overshoot or lightning strike), you want to ensure that the dielectric will not break down.
so having this standoff 300V is extreamly questionable, but on a system that operated at say 250V MAX but transient to say 350… sure (NOTE: I wouldn’t dream of putting a 0805 across 300V … even if creep&clearance appears ok, even with parylene conformal coating )
Likewise treating this part as a discussion point, just because it is rated for 500V does not mean you would put it into a system with 500V because it is never good to run a part at 100% rating
I’ve written up a little bit about clearance matrix specification using the new design rules system. It’s not reviewed yet, but should give an idea what working with v6 will look like:
I also started a thread here, which seems to have been missed due to missing keywords ^^
One can specify zones on on a user layer dedicated to conformal coating / underfill / glob top encapsulation (e.g. calling them Encapsulation1, Encapsulation2, …), and then localize clearance rules via