Pretty much this, but even then it is questionable.
If you are dealing with a couple sure you can deal with this. But at a large automated assembler or on a shop floor…
I would question whether parylene would get under the component. This is why I simply don’t take the risk.
As to the new design rules, this is the only thing that has me really excited with regards to V6. I have 4 cards I am just tidying up for release and then I want to fork my repositories and start playing with V6. Presently all 4 are a mish mash of keep out zones or relying on eyeballing and measuring… Not idea but it works.
Things are being tidied up and some issues found and solved as we speak. It’s the right time to start playing with it, but I wouldn’t rely on it to be 100% water tight yet. A few more weeks and it’s going to be awesome.
There are some interesting open questions when it comes to design rules and creepage, of all things. I’ve brushed up against it trying isolation slots.
I only tried parylene insulation twice, and it was probably way too thin to be relevant.
Underfill should work coming from an automatic dispenser, if you can make the inspection afterwards happen (SAM).
You might also find these interesting - there are quite a few ideas out there that might help solve the problem. Of course, the clearance choke points still need to be consciously permitted (for example by creating modified footprints with encapsulated modified clearance zones), but at least then we’d be out of the uncanny workaround valley.
“A simple version would be to define an area where all constraint are set to
default, better solution is to define acceptable size in this area.”
“It would be nice to have the option of setting a start and end line width
for individual segments in pcbnew. This would be a smooth taper from a
wide, low-impedance trace to a narrower trace. Note, the taper should have
an option for linear or curved.”
“In Kicad 5 all traces have round ends. In some cases it is necessary (or at
least desirable) to have precise square ends that coincide with the
endpoint’s X and Y.”
FWIW I have just checked IEC62368 for creepage and clearance requirements:
Creepage, assuming pollution degree 2 and material group III (typical PCB material) boils down to 1mm per 100V RMS working voltage above 200V
Clearance, 0.2mm for basic or supplementary insulation, 0.4mm for reinforced insulation up to 800V peak working voltage
For those unfamiliar, IEC62368 is the go to standard for safety for most electronics and completely supersedes the now obsolete IEC60950 and IEC60065
As pointed out elsewhere the capacitor alone probably meets the requirements of the standard since creepage on a ceramic surface in a PD 1 environment is reduced to the clearance distance so the limit becomes the dielectric breakdown voltage
One feature that might be worth thinking about is something to automatically set clearances based on peak voltage and whatever standard one might apply (or just pick one). This has the advantage of simplicity, and not relying on a setting a matrix of clearances for lots of different net classes. Clearance would be specified by relative voltage, as it should be.
For example, Net1 is set to 100V, and Net2 to 200V. The clearance between Net1 and GND is 1mm, the difference between Net2 and GND is 2mm, but the clearance between Net1 and Net2 is 1mm. (This is something I face when using multiple resistors in series over high voltages.)
Just a thought, I’m sure there are problems with it.
I recently worked on a B6 bridge board that immediately had to incorporate clearance matrix information, so I should mention two aspects:
When using a sparse definition of self-clearance and mutual clearance values per net class, a pretty straight-forward block matrix form emerges, where the diagonal elements are low voltage clearance and the off-diagonal ones are all the same value of high voltage clearance.
Since the definition is pretty repetitious and a common case for multi-phase high voltage circuits, a template construct is proposed in https://gitlab.com/kicad/code/kicad/-/issues/5696 . I’m confident that it’ll take most of the lead out of clearance matrix definitions, while not compromising the power of rule scripting.
For example, Net1 is set to 100V, and Net2 to 200V. The clearance between Net1 and GND is 1mm, the difference between Net2 and GND is 2mm
This seems like an intrinsically 1D description for a 2D problem, so some translation is necessary. For simple cases, this seems akin to nesting clearances to avoid clearance specifications towards multiple other net classes. Unfortunately, there’s a catch: clearances aren’t signed, so two resistive dividers from GND to HV would each cause HV to be the innermost net class, and have twice the maximum clearance from itself than from GND.
One could also think of a clearance matrix tool that derives clearance matrix elements from voltage ranges specified for each net class w, with respect to a common reference potential.
With all that work put into the definitions, there might still be some additional information missing: what about voltage transients? Are there some correlated potentials?
Here’s another thought:
At least in power electronics, one can imagine sets of nets that have smaller clearances among each other and are localized in one region of the board, while keeping a substantial distance from any other net in the design. In that sense, grouping net classes and specifying clearances with respect to such a group would be physically plausible while being almost equivalent to a block matrix formulation in the clearance matrix - only that one wouldn’t need to fill in so many fields with mostly redundant clearance values. It is then up for debate whether this is a true case of nesting.
Finally, clearance constraints are not just about the 2D clearance matrix. Localizing clearances to individual layers makes it 3D, and including inter-layer constraints blows that up to 4D. So the general case already is that definitions are sparse in nature, and one should look for ways to better describe the rules in an abstract way. Net class grouping may be an ingredient, but it may be more of a shorthand notation for clearances than a general solution.
Pretty sure this is also for Basic or Supplementary insulation (at least it is in IEC61010), so it applies only where insulation failure would present a safety hazard. The IEC/EN standards rarely say much about Functional insulation - they don’t care whether your dingus works or not, as long as it doesn’t present a safety hazard. The IPC guidelines are more conservative, and more concerned with proper functionality and reliability.
