I've saved the DRU file from Eagle after entering identifying numbers so I can associate each dialog entry box to its corresponding token in the DRU file. The following is a list of those tokens written by the current copy of Eagle with the explanations within the Eagle dialogs/tabs.
One issue is that some KiCad "rules" are entries that determine future placements (Global Settings of pads/mask/paste clearance). After placement, any of those items can be changed. There does seem to be few actual DRC checks (mostly those under Global Design Rules).
Here is the annotated DRU file, with my comments preceded by ***
I'll be breaking this down further (later) to figure out what and how to implement.
description[de] = <b>EAGLE Design Rules</b>\n<p>\nDie Standard-Design-Rules sind so gewählt, dass sie für \ndie meisten Anwendungen passen. Sollte ihre Platine \nbesondere Anforderungen haben, treffen Sie die erforderlichen\nEinstellungen hier und speichern die Design Rules unter \neinem neuen Namen ab.
description[en] = <b>EAGLE Design Rules</b>\n<p>\nThe default Design Rules have been set to cover\na wide range of applications. Your particular design\nmay have different requirements, so please make the\nnecessary adjustments and save your customized\ndesign rules under a new name.
layerSetup = (1*16)
mtCopper = 0.11mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.13mm
mtIsolate = 0.12mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm
# CLEARANCE Tab
# Minimum Clearance between objects in signal layers.
# The Same Signals check between Smd and Via does not apply to Micro Vias
# The Same Signals check does not apply if an Smd and Smd/Pad are in the same package.
# Setting the values for the Same Signals checks to 0 disables the respective check.
# WireWire could be checked against Net Classes Clearance
mdWireWire = 14mil # Clearance, Different Signals
mdWirePad = 15mil # Clearance, Different Signals
mdWireVia = 1mil # Clearance, Different Signals
mdPadPad = 17mil # Clearance, Different Signals
mdPadVia = 18mil # Clearance, Different Signals
mdViaVia = 19mil # Clearance, Different Signals
mdSmdPad = 21mil # Clearance, Same Signals
mdSmdVia = 22mil # Clearance, Same Signals
mdSmdSmd = 20mil # Clearance, Same Signals
# Not directly in dialog
mdViaViaSameLayer = 8mil # Calculated? How?
mnLayersViaInSmd = 2 # Calculated? How?
# DISTACE Tab
# Minimum Distance between objects in signal layers (pads, smds and any copper connected to them) and the board dimensions, and between drill holes.
# Setting the value for the Copper/Dimension check to 0 disables that check.
mdCopperDimension = 23mil # *** Any Copper to Board Edge (i.e. Edge Cut overlap of Margin)
mdDrill = 24mil # *** Minimum Drill Hole-Hole Distance
mdSmdStop = 0mil # Calculated? How?
# SIZES Tab
# Minimum Sizes of objects in signal layers and of drill holes.
# Minimum Width and Minimum Drill may be overwritten by larger values in the Net Classes for specific signals.
# Min. Micro Via applies to blind vias that are exactly one layer deep. Typical values are in the range 50-100 micron. The value has to be smaller than Minimum Drill; otherwise (e.g. with the default value of 9.99mm) there are no micro vias defined.
# Min. Blind Via Ratio defines the minimum drill diameter d a blind via must have if it goes through a layer of thickness t. Board manufacturers usually give this "aspect ratio" in the form 1:0.5, where 0.5 would be the value that has to be entered here.
# *** EAGLE seems to define uVia as blind vias. KiCad has separate checkboxes to "Allow blind/buried vias" and "Allow micro vias (uVias)".
msWidth = 25mil # *** Minimum Width - GDR Minimum track width
msDrill = 26mil # *** Minimum Drill - GDR Minimum Via drill
msMicroVia = 27mm # Min. Micro Via *** GDR Minimum uVia drill (blind via one layer deep, usually 50-100um); Allow micro vias if msMicroVia < msDrill
msBlindViaRatio = 28.000000 # Min. Blind Via Ratio (thickness=1:diameter=x)
# RESTRING Tab
# Restrings for pads and vias are defined in percent of the drill diameter (limited by Min and Max). If the diameter of an actual pad or via would result in a larger restring, that value will be used in the outer layers.
# If the Diameter option is checked the actual pad or via diameter will be taken into account in the inner layers, too.
# Micro Vias are blind vias that are exactly one layer deep and have a drill diameter that is smaller than the Minimum Drill value defined under Sizes (which may be overwritten by a larger Drill value in the Net classes).
# *** Essentially, this appears to be a variety of Annular ring sizes
# *** in KiCad, this is expressed as Via/Pad Size vs ViaPad DrillSize/DrillValue
# The Net Classes could be checked against this (Via Dia, Via Drill (and uVia) And individual vias could all be checked for this.
# % (value on display is '30', which is converted to 0.30)
rvPadTop = 0.300000
rvPadInner = 0.330000
rvPadBottom = 0.360000
rvViaOuter = 0.390000
rvViaInner = 0.420000
rvMicroViaOuter = 0.450000
rvMicroViaInner = 0.480000
# Min/Max values
rlMinPadTop = 29mil
rlMaxPadTop = 31mil
rlMinPadInner = 32mil
rlMaxPadInner = 34mil
rlMinPadBottom = 35mil
rlMaxPadBottom = 37mil
rlMinViaOuter = 38mil
rlMaxViaOuter = 40mil
rlMinViaInner = 41mil
rlMaxViaInner = 43mil
rlMinMicroViaOuter = 44mil
rlMaxMicroViaOuter = 46mil
rlMinMicroViaInner = 47mil
rlMaxMicroViaInner = 49mil
# SHAPES Tab
# *** Not sure yet how KiCad handles rounded rectangles.
# Shapes of pads and smds
srRoundness = 0.510000 # Smds %
srMinRoundness = 50mil # Smds Min
srMaxRoundness = 52mil # Smds Max
psTop = -1 # As in library
psBottom = 0 # Square
psFirst = 1 # round
# *** Elongation refers to the pad rounded rect length vs drill diameter.
# *** This doesn't seem supported in KiCad.
psElongationLong = 53 # %?
psElongationOffset = 54
# MASKS Tab
# Mask values are defined in percent of the smaller dimension of smds, pads and vias (limited by Min and Max).
# Stop masks are generated for smds, pads and those vias that have a drill diameter that exceeds Limit
# Cream masks are generated for smds only.
# *** Stop = Solder Mask; Cream = Paste
# *** Min <= copperMin(L,W)*% <= Max
# *** copperMin is KiCad Pad Size
# *** Not sure if there's a max of copperMax(L,W)
# *** These are directly related to pad properties
# *** and can be checked in layout:
# *** Solder mask clearance,
# *** Solder paste clearance,
# *** Solder paste ratio clearance
# *** This KiPadCheck plugin territory
mvStopFrame = 0.570000 # %
mvCreamFrame = 0.600000 # %
mlMinStopFrame = 56mil
mlMaxStopFrame = 58mil
mlMinCreamFrame = 59mil
mlMaxCreamFrame = 61mil
mlViaStopLimit = 62mil *** What is this? (listed on screen as 'Limit')
# SUPPLY Tab
# The Thermal isolation parameter is used when substracting pad shapes from signal polygons
# If Generate thermals for vias is checked, vias will be connected to signal polygons via thermals.
# *** KiCad: Dimensions > Pads > Local Clearance and Settings:
# *** Thermal Relief Width and Select "Pad Connection" = "Thermal Relief"
slThermalIsolate = 55mil
slThermalsForVias = 0
# MISC Tab
# The Grid check verifies that all pads, smds, vias and wires in signal layers are on the current grid.
# The Angle check reports signal wires that are not placed in multiples of 45 degrees.
# The Gap factor is multiplied with the clearance used in the differential pair and determines the distance between the loops of the meander.
*** KiCad Dimensions > Differential Pair > Width and Trace Gap and optional Via Gap
dpMaxLengthDifference = 63mm # in differential pairs
dpGapFactor = 6.400000 # for meanders in differential pairs
checkGrid = 0
checkAngle = 0
checkFont = 1
checkRestrict = 1
# Not in dialog box
useDiameter = 15
maxErrors = 50