Design Rules File load/save


#1

Does a design rules file load/save functionality exist?

I’ve started a python script but wondering if someone has already tackled it.

Hopefully this will help to set up design rules for different shops! Importing their rules instead of a KiCAD template.

Here’s the very beginning:

class design_file():
    def read(self,filename):
        print("Reading: %s\n"%filename)
        with open(filename) as file:
            for line in file:
                eqindex = line.index('=')
                token = line[0:(eqindex-1)].strip()
                if token == "":
                    break;
                print("Unsupported token: %s"%token)
        print("Done.\n")
        return
    def save(self,file):
        return

I’m designing it so it reads/writes EagleCAD *.dru files. Well, at least the tokens in these files:
http://www.eurocircuits.com/eagle-dru-files/


Anyone installed NumPy for use with KiCAD's python?
Units for data entry
Edit design rules with script
#2

Here’s the output of the above code with one of the .dru files from eurocircuits:

Reading: eC_2Layer_PClass6_BaseCopperO18_eCDefault.dru

Unsupported token: description[de]
Unsupported token: description[en]
Unsupported token: layerSetup
Unsupported token: mtCopper
Unsupported token: mtIsolate
Unsupported token: mdWireWire
Unsupported token: mdWirePad
Unsupported token: mdWireVia
Unsupported token: mdPadPad
Unsupported token: mdPadVia
Unsupported token: mdViaVia
Unsupported token: mdSmdPad
Unsupported token: mdSmdVia
Unsupported token: mdSmdSmd
Unsupported token: mdViaViaSameLayer
Unsupported token: mnLayersViaInSmd
Unsupported token: mdCopperDimension
Unsupported token: mdDrill
Unsupported token: mdSmdStop
Unsupported token: msWidth
Unsupported token: msDrill
Unsupported token: msMicroVia
Unsupported token: msBlindViaRatio
Unsupported token: rvPadTop
Unsupported token: rvPadInner
Unsupported token: rvPadBottom
Unsupported token: rvViaOuter
Unsupported token: rvViaInner
Unsupported token: rvMicroViaOuter
Unsupported token: rvMicroViaInner
Unsupported token: rlMinPadTop
Unsupported token: rlMaxPadTop
Unsupported token: rlMinPadInner
Unsupported token: rlMaxPadInner
Unsupported token: rlMinPadBottom
Unsupported token: rlMaxPadBottom
Unsupported token: rlMinViaOuter
Unsupported token: rlMaxViaOuter
Unsupported token: rlMinViaInner
Unsupported token: rlMaxViaInner
Unsupported token: rlMinMicroViaOuter
Unsupported token: rlMaxMicroViaOuter
Unsupported token: rlMinMicroViaInner
Unsupported token: rlMaxMicroViaInner
Unsupported token: psTop
Unsupported token: psBottom
Unsupported token: psFirst
Unsupported token: psElongationLong
Unsupported token: psElongationOffset
Unsupported token: mvStopFrame
Unsupported token: mvCreamFrame
Unsupported token: mlMinStopFrame
Unsupported token: mlMaxStopFrame
Unsupported token: mlMinCreamFrame
Unsupported token: mlMaxCreamFrame
Unsupported token: mlViaStopLimit
Unsupported token: srRoundness
Unsupported token: srMinRoundness
Unsupported token: srMaxRoundness
Unsupported token: slThermalIsolate
Unsupported token: slThermalsForVias
Unsupported token: dpMaxLengthDifference
Unsupported token: dpGapFactor
Unsupported token: checkGrid
Unsupported token: checkAngle
Unsupported token: checkFont
Unsupported token: checkRestrict
Unsupported token: useDiameter
Unsupported token: maxErrors
Done.


#3

Not really. (At least not yet.)

The only option is a so called template.
You can use the pcb_new file of the template to store this information.


#4

Thanks, Rene!

That’s what I had thought I read in another forums conversation. It seems like it still would be useful to read from a manufacturer-supplied rules file.


#5

I bet the developers welcome volunteers. (I seem to remember reading somewhere that it is planned for the future but don’t hold your breath. It might take a while.)


#6

Yes, they seem to welcome volunteers. The main suggestion they had was to determine interest and work with testers outside of the developers mailing list (which I’m guessing means these forums).

Once it’s developed enough, then submit to launchpad or github, and notify the developers mailing list.

This is my post gauging interest (and see if it’s duplicating something else) and will be developing the python script to implement the functionality.

Thank you!!


#7

At the present time, the KiCAD global design rules are rather minimal - minimum trace width, copper spacing, and soldermask clearance - so I don’t think a “Design Rules” file would save much effort.

Expanding the list of parameters that are considered to be “global design rules” would require expanding the scope of the DRC feature as well. (It’s not truly a “rule” if it isn’t checked and enforced.) I suspect there is currently little support among the developers for this level of effort.

Dale


#8

I think there is something planned. Not really sure what exactly though.
http://docs.kicad-pcb.org/doxygen/v6_road_map.html#v6_drc_improvements


#9

Dale,

Agreed. I thought the support for many DRC checks was minimal or nonexistant as well. That’s why I’m planning to integrate the load/save Design Rules with the KiPadCheck script I’m writing (still working out the best name). The KiPadCheck script adds checks for Annular Rings, Silk Screen, Paste, Mask, Drill layers.

Once I get through the first level of token evaluation, I’ll be able to see what DRCs are missing and possibly fill in the gaps.

It’d be great if there were interest in the programs. I’m in the middle of modifying KiPadCheck for conformance to Code Guidelines, as well as support for Action Plugin for python script support .

Greg S.


#10

Will it check for Silk Screen violations on exposed copper? If it can do that quickly and EASILY it would be a very welcome extension! (This exact problem was reported just today: How Long Looking for Errors or Improvements VS Spinning Again? )

Dale


#11

Quickly (in the sense of execution time) and python are a bit of a contradiction. Python has its strengths. Efficient code execution is not one of them. (The problem with interpreted languages.)


#13

Dale, I’ll see what’s available. First silk screen checks will be upper/lower limits on character height, character width, aspect ratio, and character thickness. I have to see what is available in the python API for actually obtaining character segments. If that is available, I can iterate through those silk screen line segments vs the tracks (I already iterate over and check tracks vs. vias).

Hopefully!


#14

Rene, the python script for drill DRC (check via drill to via drill spacing and via drill to track spacing) takes about 13.5 seconds on a board with the following characteristics:
size: about 75mm x 75mm, 1 layer checking at the moment.
293 pads
109 vias
1684 track segments
283 nodes
92 nets


#15

Dale and Rene,

Performance for checking Silk overlap of Mask (i.e. exposed copper) is excellent in python.
Loading the script and executing is about 300 milliseconds

Same board as before (75mm x 75mm), comparing
Front pads=293 text=57
Back pads=72 text=19

This turns out to be over 18000 checks.

Even if I figure out how to do the geometric shapes, I just can’t see this particular check taking a significant amount of time. Note that this was checking the bounding boxes of the text vs. pad. Which will generally work if your text and pads are orthogonal.

So far so good!


#16

I tried implementing some of the Eagle design rules in my Eagle conversion took (eakit). Eagle has a lot more rules than KiCad, and the way they are implemented is somewhat different. There are also some strange quirks in the Eagle rules.

However, being able to export/import KiCad rules would be quite useful I think.


#17

Do you have any references to the exact meaning of each token in the .dru files? All I can go on at the moment is comparing dru files with PDF and guessing.


#18

Only the help available within Eagle.


#19

Dale, I’ve made progress on the silk / exposed copper checker. I can now decode text objects into their properly rotated bounding box. Next is to figure out how to determine if two polygons intersect. I already have code to detect intersecting orthogonal rectangles, but a rotated bounding box is more like a generalized polygon. The time consuming code is when checking against all tracks. That won’t be necessary when just checking for exposed copper (I.e. Mask layers).


#20

I would like to be able to change the pcbnew DRC settings for another use-case. I have designs that have fine-pitched BGAs which require different DRC rules within the BGA area than the rest of the board. (Note, sometimes these rules are on the same nets).

Currently, I set the DRC to the tighter requirements to route the BGA escape routing, then manually change the DRC values and do the rest of the board. I run the DRC itself twice in the same way, checking errors inside the BGA zone, then outside. Being able to change between two DRC sets within pcbnew would be great, as I think it will be a while before we see area-base DRC rules.


#21

I’ve saved the DRU file from Eagle after entering identifying numbers so I can associate each dialog entry box to its corresponding token in the DRU file. The following is a list of those tokens written by the current copy of Eagle with the explanations within the Eagle dialogs/tabs.

One issue is that some KiCad “rules” are entries that determine future placements (Global Settings of pads/mask/paste clearance). After placement, any of those items can be changed. There does seem to be few actual DRC checks (mostly those under Global Design Rules).

Here is the annotated DRU file, with my comments preceded by ***

I’ll be breaking this down further (later) to figure out what and how to implement.

description[de] = <b>EAGLE Design Rules</b>\n<p>\nDie Standard-Design-Rules sind so gewählt, dass sie für \ndie meisten Anwendungen passen. Sollte ihre Platine \nbesondere Anforderungen haben, treffen Sie die erforderlichen\nEinstellungen hier und speichern die Design Rules unter \neinem neuen Namen ab.
description[en] = <b>EAGLE Design Rules</b>\n<p>\nThe default Design Rules have been set to cover\na wide range of applications. Your particular design\nmay have different requirements, so please make the\nnecessary adjustments and save your customized\ndesign rules under a new name.
layerSetup = (1*16)
mtCopper = 0.11mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.13mm
mtIsolate = 0.12mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm

# CLEARANCE Tab
# Minimum Clearance between objects in signal layers.
# The Same Signals check between Smd and Via does not apply to Micro Vias
# The Same Signals check does not apply if an Smd and Smd/Pad are in the same package.
# Setting the values for the Same Signals checks to 0 disables the respective check.

# WireWire could be checked against Net Classes Clearance
mdWireWire = 14mil # Clearance, Different Signals
mdWirePad = 15mil # Clearance, Different Signals
mdWireVia = 1mil # Clearance, Different Signals
mdPadPad = 17mil # Clearance, Different Signals
mdPadVia = 18mil # Clearance, Different Signals
mdViaVia = 19mil # Clearance, Different Signals
mdSmdPad = 21mil # Clearance, Same Signals
mdSmdVia = 22mil # Clearance, Same Signals
mdSmdSmd = 20mil  # Clearance, Same Signals

# Not directly in dialog
mdViaViaSameLayer = 8mil # Calculated? How?
mnLayersViaInSmd = 2     # Calculated? How?

# DISTACE Tab
# Minimum Distance between objects in signal layers (pads, smds and any copper connected to them) and the board dimensions, and between drill holes.
# Setting the value for the Copper/Dimension check to 0 disables that check.
mdCopperDimension = 23mil # *** Any Copper to Board Edge (i.e. Edge Cut overlap of Margin)
mdDrill = 24mil      # *** Minimum Drill Hole-Hole Distance

mdSmdStop = 0mil # Calculated? How?

# SIZES Tab
# Minimum Sizes of objects in signal layers and of drill holes.
# Minimum Width and Minimum Drill may be overwritten by larger values in the Net Classes for specific signals.
# Min. Micro Via applies to blind vias that are exactly one layer deep. Typical values are in the range 50-100 micron. The value has to be smaller than Minimum Drill; otherwise (e.g. with the default value of 9.99mm) there are no micro vias defined.
# Min. Blind Via Ratio defines the minimum drill diameter d a blind via must have if it goes through a layer of thickness t. Board manufacturers usually give this "aspect ratio" in the form 1:0.5, where 0.5 would be the value that has to be entered here.
# *** EAGLE seems to define uVia as blind vias. KiCad has separate checkboxes to "Allow blind/buried vias" and "Allow micro vias (uVias)".
msWidth = 25mil # *** Minimum Width - GDR Minimum track width
msDrill = 26mil # *** Minimum Drill - GDR Minimum Via drill
msMicroVia = 27mm # Min. Micro Via *** GDR Minimum uVia drill (blind via one layer deep, usually 50-100um); Allow micro vias if msMicroVia < msDrill
msBlindViaRatio = 28.000000 # Min. Blind Via Ratio (thickness=1:diameter=x)

# RESTRING Tab
# Restrings for pads and vias are defined in percent of the drill diameter (limited by Min and Max). If the diameter of an actual pad or via would result in a larger restring, that value will be used in the outer layers.
# If the Diameter option is checked the actual pad or via diameter will be taken into account in the inner layers, too.
# Micro Vias are blind vias that are exactly one layer deep and have a drill diameter that is smaller than the Minimum Drill value defined under Sizes (which may be overwritten by a larger Drill value in the Net classes).

# *** Essentially, this appears to be a variety of Annular ring sizes
# *** in KiCad, this is expressed as Via/Pad Size vs ViaPad DrillSize/DrillValue
# The Net Classes could be checked against this (Via Dia, Via Drill (and uVia) And individual vias could all be checked for this.

# % (value on display is '30', which is converted to 0.30)
rvPadTop = 0.300000 
rvPadInner = 0.330000
rvPadBottom = 0.360000
rvViaOuter = 0.390000
rvViaInner = 0.420000
rvMicroViaOuter = 0.450000
rvMicroViaInner = 0.480000

# Min/Max values
rlMinPadTop = 29mil
rlMaxPadTop = 31mil
rlMinPadInner = 32mil
rlMaxPadInner = 34mil
rlMinPadBottom = 35mil
rlMaxPadBottom = 37mil
rlMinViaOuter = 38mil
rlMaxViaOuter = 40mil
rlMinViaInner = 41mil
rlMaxViaInner = 43mil
rlMinMicroViaOuter = 44mil
rlMaxMicroViaOuter = 46mil
rlMinMicroViaInner = 47mil
rlMaxMicroViaInner = 49mil

# SHAPES Tab
# *** Not sure yet how KiCad handles rounded rectangles.
# Shapes of pads and smds
srRoundness = 0.510000 # Smds %
srMinRoundness = 50mil # Smds Min
srMaxRoundness = 52mil # Smds Max

psTop = -1 # As in library
psBottom = 0 # Square
psFirst = 1 # round

# *** Elongation refers to the pad rounded rect length vs drill diameter.
# *** This doesn't seem supported in KiCad.
psElongationLong = 53 # %?
psElongationOffset = 54

# MASKS Tab
# Mask values are defined in percent of the smaller dimension of smds, pads and vias (limited by Min and Max).
# Stop masks are generated for smds, pads and those vias that have a drill diameter that exceeds Limit
# Cream masks are generated for smds only.

# *** Stop = Solder Mask; Cream = Paste
# *** Min <= copperMin(L,W)*% <= Max 
# *** copperMin is KiCad Pad Size
# *** Not sure if there's a max of copperMax(L,W)
# *** These are directly related to pad properties
# *** and can be checked in layout:
# ***    Solder mask clearance, 
# ***    Solder paste clearance,
# ***    Solder paste ratio clearance
# *** This KiPadCheck plugin territory
mvStopFrame = 0.570000 # %
mvCreamFrame = 0.600000 # %
mlMinStopFrame = 56mil
mlMaxStopFrame = 58mil
mlMinCreamFrame = 59mil
mlMaxCreamFrame = 61mil

mlViaStopLimit = 62mil *** What is this? (listed on screen as 'Limit')


# SUPPLY Tab
# The Thermal isolation parameter is used when substracting pad shapes from signal polygons
# If Generate thermals for vias is checked, vias will be connected to signal polygons via thermals.
# *** KiCad: Dimensions > Pads > Local Clearance and Settings:
# *** Thermal Relief Width and Select "Pad Connection" = "Thermal Relief"
slThermalIsolate = 55mil
slThermalsForVias = 0

# MISC Tab
# The Grid check verifies that all pads, smds, vias and wires in signal layers are on the current grid.
# The Angle check reports signal wires that are not placed in multiples of 45 degrees.
# The Gap factor is multiplied with the clearance used in the differential pair and determines the distance between the loops of the meander.

*** KiCad Dimensions > Differential Pair > Width and Trace Gap and optional Via Gap
dpMaxLengthDifference = 63mm # in differential pairs
dpGapFactor = 6.400000 # for meanders in differential pairs

checkGrid = 0
checkAngle = 0
checkFont = 1
checkRestrict = 1

# Not in dialog box
useDiameter = 15
maxErrors = 50

DRC: Drill to Track clearance?