Title says it all. For example, looking at this capabilities, many of it are not available in KiCad I suppose.
How can those be taken care of ? Specifically:
- Drill to Track clearance
- Drill to Drill clearance
- Minimum Drill size for plated hole
Not really, it lacks an interrogative and a verb!
Anyway, KiCad has only one type of clearance, so choose that for whatever you want. There is a min size for vias, but not for PTH holes in general.
@HiGreg is working on an enhanced DRC script, maybe he has some ideas.
I think any clearance that is added to drc needs to be added at a low enough level such that the interactive router has access to it. A python script that checks it afterwards is a possible workaround but it can not be the end goal. (Checking silk screen pad overlaps is different in this regard.)
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?!?
KiCAD specs the final size of the plated hole, no idea what ‘minimum’ in this context means.
As ‘drills’ (just holes or are we talking PTH here?) will have annular copper around them, the track clearance will be obeyed
?!?
What is that used for?
If they are PTHs, the track clearance will keep the copper apart, no idea what else would be needed.
As for internal clearances for inner layers - yes, KiCAD can’t do that yet - there was some talk about a drill-stack to be implemented at some point (different clearances for different layers with different annular rings for different nets, etc., the whole shebang), but I haven’t heard anything about it in the wild (yet).
Might need to search the developer forum on that one, to get a status update…
I think we decided the industry convention is that “drill size” is equivalent to “finished hole size” for PTH.
As I know that you know, holes are made in a separate process to etching copper, so there is likely a larger spacing required for hole->Cu than Cu-Cu.
Some people use overlapping drill hits to create slots, also mouse bites.
I’m fairly sure most of these values are important to the manufacturer, otherwise they would not specify them.
It would be great to have these features.
Thanks for all the suggestions.
Hm. Normally you define drill holes as a footprint (< 6.35 mm).
If you need a special clearance for them to copper, just adjust the local clearance for those NPTHs?
For that matter, clearance to board-edge can’t be set in KiCAD either… 
The clearance for PTHs should be determined by the annular copper anyway.
But I get that inner layers demand a bigger clearance than the outer layers, because of layer-layer-placement tolerances… KiCAD can’t do that yet.
That’s why I asked what kind of drills we’re talking about here.
And using overlapping drills for slots is just really really bad practice. Drills are drills and not milling bits.
If one needs slots they should be created via milling and defined accordingly.
Overlapping drills is begging for trouble.
Any fabricator who can’t mill slots or any ECAD tool that can’t define milling slots (plated/unplated) should not be used anymore IMHO. We’ve got 2017, not 1967 
And placing drills close together, again, we got the drill clearance that we can set, as well as give us some human help by drawing a circle on the x.Fab layer to define a clearance area for the drill footprint. All my NPTH footprints have that.
Oh yeah, I’m with you on that! 
I’ve seen the overlapping drills method being advised as a way to do slots, while converting to KiCad I discovered that the Arduino Uno uses that method:
So far, I’ve not had any major screw ups, but I mainly do cheap noddy stuff.
KiPadCheck can check drill-drill spacing. I’m also working on DRC Load / Save. That thread contains reference to EAGLE DRU files. In particular the layer definitions section (shown is two copper layers): (these are EAGLE DRC screenshots):
And the REST-RING section with DRC rules for inner/outer/top/bottom annular rings for pads/vias/uvias.
And the sizing for drill sizes:
My belief is that the layer thicknesses are specified exactly because the Blind Via Ratio check here. I don’t see anywhere else that would be useful (besides the 3d viewer).
I am trying to figure out what makes sense to implement in KiPadCheck.
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I’ve added Drill to Edge.Cuts spacing check in the development version of KiPadCheck. Let me know if you want me to push it to GitHub for testing.
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Yes please (If it is not already done.)
Your script is definitely a good addition to kicads limited drc capabilities.
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Funny, I thought it was re-string. I’ve never heard the term “rest-ring” used before, does it make more sense in German? I’ve always seen it referred to as “annular ring”.
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I just learned the term recently as well. I got it from the EAGLE DRCs, particularly this post: “The Restring (it’s pronounced: rest-ring ) settings are used for calculating the diameter of through hole pads in the Layout Editor only.”
It totally makes sense in English, but I’ve only heard it called “annular ring” like yourself.
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It doesn’t make any sense in English though, for any common meanings of “rest”…unless it is a place where the electrons go to have a snooze?
I was thinking for screw/bolt holes, where the screw head rests. But maybe that’s a stretch. Perhaps it’s where the copper rests on the surface of the core or prepreg (e.g. FR4)?
German would be “Kupferrestring”. Direct translation (word by word): remaining copper ring.
So as you guessed correctly it makes sense in German.
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Ah, so it’s “the ring remaining after the hole has been drilled”. Reminds me of Rechtsschutzversicherungsgesellschaften
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Jay,
I also noticed your bug report about DRC rule for exposed track through soldermask . In the development version of KiPadCheck (not yet released), I’ve added a check to flag any track within a specified distance (including zero) of the solder mask that is not the same net as the pad. As with any checks relative to all tracks, it takes a noticable amount of time (100 seconds on my 75mm x 75mm test board with 1735 track segments and 329 pads).
It will be included in the next github release of the nightly-compatible KiPadCheck.
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Thank you very much for caring about Kicad’s DRC and digging up that lonely bug report!
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