As shown in the image, the outer pads will take an offset track not going to the centre of the pad, but I am trying to start on the second pad from the top right, and I get the error “Routing start point violates DRC”. As you can see by the ratsnest, there is a Schematic. I need to go out from the footprint to a via and then connect to the blue underside track above.
The 2 topside red tracks on this righthand side are 0.2mm wide. I have the global minimum copper clearance set at 0.2 mm.
Also, the red topside track from the device above won’t connect to the second pad on the left.
The footprint was downloaded from the internet and says it was generated with kicad-footprint-generator ipc_gullwing_generator.py
Don’t leave those offset tracks, as that is very bad form. Also don’t come out of a pad at 45 degrees, which not only looks bad but is an issue since etch acid does not always clean out of these acute angle spots.
You can drag your tracks around after routing them, and tidy things up. Try it. just grab a track segment and click-drag. You should be able to drag the offset tracks down towards the pad and center them. Or start your route at the chip pad so it is always correct.
If you post your project (or a trimmed-down version) maybe someone can help understand your issue more.
Thank you. I am downloading 7.0.11 (no trace of a higher version 7 on the macOS All Stable Releases page, or anywhere in the blog). I hope the newer footprint resolves this problem.
Thanks for these very valuable tips. Much appreciated. I am used to dragging things around to tidy up, but a bit of forthright comment is very helpful.
Unfortunately the project is commercially sensitive, so I can’t easily upload a sample.
I just can’t understand what could be the cause of the problem, but hopefully the footprint within a newer version 7 will resolve it.
Kinda looks like your schematic connections differ from what you are trying to route. The ratsnest wire from pin 8 is zooming down to bottom left – is it not connected to the 3.3V net? Is pin 6 also connected to it? It will not let you route to the wrong pad.
Clearance lines are not shown in the footprint editor, because they are unknown at that time. They are determined by settings in the PCB editor. Sometimes it’s from the design rules you’ve shown. More often it is as a result of the net class settings.
You can select one or more things, and then PCB Editor / Inspect / Clearance Resolution to get more info. Or simpler, just run DRC.
@teletypeguy yes that ratsnest link from pin 5 does zoom off stage left. That’s because there is another 3v3 down there that needs linking in.
In that screen grab, I’m trying to initiate a new wire from pin 6 (between the green colored pads) using a via to link to the underside blue wire top right.
@jmk I have now updated to 7.0.11 as suggested, and chosen the footprint from the library (Package_SO:MSOP-8_3x3mm_P0.65mm), but still the same problem. @paulvdh pointed out the overlapping clearance lines, and they are still there with the new footprint. It seems that is the problem, but I can’t see where to change it.
Paul mentioned net-classes and perhaps that is it. Those overly-fat i2c traces perhaps have net class constraints that over-rode the default clearance. Peek at the pcb-setup/netclass dialog, or maybe try deleting those fat i2c tracks and the footprint and update from schematic again.
Partially solved at last. It is a Design Rules issue, but not the general minimum constraints. I needed a new Pre-Defined Size track of 0.3 mm width and 0.2 mm Clearance (I called it Fine), and then to make sure all the pads in that MSOP device had associated Net Classes which required that Fine track size.
Since there is a voltage pad (3v3) and a GND pad on that device, that is a problem, since other devices need larger currents on those lines, so my general setting had been for wider tracks and clearances.
But its only partially solved, because even having set the Design Rules for the 3V3 and GND net classes to my Fine track size, the clearance lines around those respective pads haven’t changed, and nor have any of the other pads whose Net Classes I have specifically set to the Fine class.
Just pad 5 the 3v3 pad allows the new track size. Pad 6 shows the acceptable clearance around it, but pad 7 GND still overlaps pad 6.
Is there any way to split a Net Class into different regions allowing different track/clearance sizes?
PCB Editor/ File / Board Setup / Design Rules / Pre-defined Sizes does have a track width, but it does not have a clearance. I mentioned: PCB Editor/ File / Board Setup / Design Rules / Net Classes, and that is a different setting. (Very different indeed).
Net Classes are a set of rules, both for track width and clearance, and you can define in the schematic which net goes to which net class. This is the normal way of defining track width and clearance. The Pre-defined Sizes is only an extra setting that makes it easier to draw some tracks that deviate from the net class settings. Study the manual and/or tutorials until you understand how these net classes work. They are an important concept in PCB design.
Thanks @paulvdh. So ‘Pattern’ is all the connections to a particular node in the ratsnest. In the Settings, I can define which Netclass (which is a group of settings covering track width, clearance, via size, …) is assigned to each pattern.
Is there a difference between Net Class and Netclass?
Is it possible to split a set of connections for one node in the ratsnest into 2 different Patterns? I need some /GND tracks to be fine, and some to be wide, to carry different currents.
Presumably my MSOP footprint had no clearance conflicts when the schematic was first converted to a board layout. At some stage that changed without me noticing, and I don’t know how to revert. What action is likely to have caused that, and when taking that action, how could I have known that it caused the conflict? If I could ascertain that, I might be able to work out the steps to undo the conflict.
The only difference I see is with or without a space in between
What is a “pattern”. I guess you mean a “net”. A net is a list of nodes (pins) that are connected together. A NetClass (Net Class) is a set of rules (track width, clearance).
In KiCad you can use net ties to split a net into sections. You can also use the pre-defined widths to make a track narrower. Or you simply draw a track somewhere on the PCB, hover over it and press e to edit it’s properties, and then change the width. If you then move the track and place it onto a pad, it will automatically become a part of the same net as that pad.
With the button below, you can switch between always using the netclass width while drawing a track, or continuing with the same width as a track that is already on the PCB when drawing tracks.
There are 3 other mentions of them in the forum, none with any helpful information.
So I still seek a method of splitting the GND and 3v3 Nets so that some have fine tracks, and some have wide tracks for lots of current.
And hopefully somehow splitting them will magically remove those wide clearance ovals around the MSOP pads.
Otherwise I have to start again from scratch and keep an eye on the MSOP each time I add a track. The board is large (675mm long, 50mm high) with lots of mechanically placed parts and up to 10 amp current. It is challenging to draw a track along that length because there is only a small window onto the board on screen, as well as then having to move the viewport to the MSOP each time for checking.
One way to get around it is to not use net classes. I have peeked at netclasses, thought I might use them for data pairs or something, but never bother to set any up. I have designed many boards quite happily just selecting the track size and via size as I route, and I can change track sizes willy-nilly (I often change sizes as I route a power tree around). I use whatever makes sense for the area of the board I am in – generally I have global board clearance set to 0.2mm, and I define track and via sizes I like. For digital stuff I usually use 0.2 tracks with 0.6/0.3 vias, analog areas usually 0.25 tracks since there’s more space, power tracks terminating at chip pads and caps are 0.3mm and short, transitioning to 0.5 and up to perhaps 1.5mm as they go further down the power tree. For power vias I generally use 1.0/0.5, 1.3/0.8 or larger. I only use a net-tie for connecting analog/digital ground, connecting signal ground to an esd ring, or other specific use cases, not in the power distribution. Just my way of doing it.
The willy-nilly approach is what I use, but it seems to be part of the problem. The original question is that I can’t route tracks on to the MSOP because at some stage, the perfectly good footprint has acquired clearance ovals on the pads which prevent tracks being made. How can I change those clearance ovals? I subsequently explicitly defined narrow tracks and small clearances for the respective nets but it has no effect.
