File > Board Setup > Design Rules > Constraints > Copper > Minimum clearance.
You posted an image of the page, in this thread, earlier. The image shows .2mm setting.
Functionally a net tie is similar to a zero ohm resistor. It can be used to split one net to two different parts (or more, forming a star connection point). In KiCad it is implemented as a footprint which ties two (or more) pads together with copper, so that the result is like zero ohm resistor/resistors without a physical component.
The current KiCad implementation is more advanced than what it was back then. You can open one of the NetTie footprints and see how itâs done. The important part is in the footprint properties:
Now I see the âpatternâ. thing. 
A pattern is a text string that is used to assign a net to a netclass.Such a pattern can also contain wildcards, so you can put a lot of nets into a netclass with a single pattern.
For your clearance problem around the pads you will have to change the clearance. At the moment just the clearance around a pad overlaps with the copper of another pad. This will always generate DRC violations.
Your MCP0808_MSOP symbol has (by default) the footprint: Package_SO:MSOP-8_3x3mm_P0.65mm assigned to it. This footprint has a pin pitch of 0.65mm, 0.4mm wide tracks, and that leaves only 0.25mm of clearance between the pads. This is not extreme, but this package is small enough that you have to be a bit careful with how you connect tracks to it.
Now you are trying to do at least 3 different things at once.You are fighting with the clearance for this footprint, and you are struggling with track widths and how to change them, and your perception of net classes and how they work is probably also not clear. Try to tackle one problem at a time.
I suggest you start with netclasses. Make a few net classes, put some tracks in each netclass, change netclass settings for track width and clearance and then see how this behaves. After that, learn how to change track widths without changing the netclass settings of that track. Put some widths in the pre-defined sizes list, and change the widths of some of the tracks. This is also a good moment to experiment with the toggle switch to use track width of an existing track that I showed earlier.
If you have done these two things, then you have enough knowledge to fix the clearance problem with your footprint. You probably also want to experiment with: PCB Editor / Preferences / Preferences / PCB Editor / Display Options / Clearance Outlines This has a selection list and a checkbox to tell KiCad when to show the clearance outlines.
This is my original schematic for the MSOP MCP9808 thermometer, which has the overlapping clearance problem.
I have edited the schematic so that all local tracks are independent by removing the 2 embedded SDA and SCL entries, and making the main 3v3 and GND connection, as well as the Alert connection, all connect to a new net called THM. The whole chip should now have none of the previous nets connected to it.
Then I updated the layout from the schematic, and for good measure I updated the thermometer footprint from the library (which obviously said no change, so no effect).
I went into to Board Setup > Design Rules > Net Classes > Netclass Assignments and set this new net THM to my Fine track with 0.2mm track and 0.2mm clearance.
I still have the clearance problem.
There seems no good reason why the clearance ovals are so large.
(I previously managed to get the top right pin 8 working using a similar trick of isolating it).
@paulvdh I totally agree about the need to focus on one thing. I have previously set individual track widths by simply double clicking on them and changing the width. I think I do know what a net is, and how to set net class values as I showed by setting the special net THM and assigning it my Fine track.
But I canât find what is causing the clearance ovals to be the size they are. My Minimum clearance is 0.2mm and so is my Minimum track width.
Itâs nice to see net names on the pads, but shorting Power and GND on this IC is not a good thing.
Note that pin 7 of your footprint now does have a narrower clearance that fits in between the pads. Creating a netclass is not enough, you also have to assign nets to your netclass. From your previous screenshots, I see you have already created a bunch of net classes (why so many?) and assigned nets to them (with the âpatternsâ).
Now your next task is to figure out why pad No 7 with the net Net-(U2-A0) has that smaller clearance. Your Fine netclass appears to be the only one with a 0.2mm clearance.
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Hmm, if it was me I would save the project with a new name for testing, delete all net-classes and see what happens.
I have removed a lot of this project, and what remains still has the problem of the clearance ovals. I attach a zip of the reduced project. This is purely to demonstrate the problem. The schematic around the MSOP thermometer has been changed to remove any extraneous connections, which is why 3v3 and GND are on the same THM net.
Main-Boardv2.0_test.zip (398.1 KB)
I still have the problem in my much larger project, and I am seeking help to resolve the problem there.
You have a very long list of names in the âpatternâ column:
Itâs good that I now see only two netclasses (Default and Fine). That avoids some causes of confusion.
There are a few weird things about your table though. First, any net that is not in this table will have the Default netclass, so you donât have to put those at all in the table.
I also see a lot of /IO* net names listed. Those can all be contracted to a single table entry by using the wildcard as I did. However, these labels are not even in your schematic, so I donât know why they are in the Netclass pattern table.
And for your immediate problem, the net names do not match, you have to put a slash in front of the THM name. Like this:
May I suggest to you to read this part of the documentation:
@paulvdh that finally resolves my problem. The Default Netclass was being applied and is too large.
I have now read the documentation and learned more about it. I think my project used an up-cycled previous project from a few years ago, because I certainly hadnât set the Default Netclass.
The default netclass is always present in each project. That is why itâs the default
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