Bus slice semantics

I’m having some trouble with bus connections as follows:

BANK0 isn’t getting any connections made to it. If I change the bus connected to BANK0 to D[15..0] then it gets copies of the BANK1 connections as I would expect.

Internals of PerBank.sch look like this:

Screen Shot 2021-04-04 at 4.38.56 AM

Further, when I tried to reverse the slice by changing the label on the bus connecting to BANK1 to D[0..15] it didn’t seem to have any effect.

I’m running the release Mac build (5.1.9-0-10_14).

Please try renaming the pin D [15…0] in BANK 0 to D [31…16]. This should solve the issue.

What @Amit_Bahl sadly does not work. Only changing the name of the hierarchical pin is sadly not enough. I fear you might need to put the full bus into both sheets and then select the lower half of the bus connectors in one sheet and the higher in the other or have the 16 pins as an input instead of a bus and do the splitting on the outside. Another workaround could be to have a splitting sheet (a sheet that takes in the full bus and then makes two new buses as the output.

See Splitting a bus in hierarchical schematic: problems

It might be the case that the new bus handling in version 6 will resolve this issue but i am not sure about that.

Could you please share the screenshots of the schematic? So that we could analyze them once.