Thanks for the reply, but I do not understand it. It sounds like you are suggesting that the sub-sheets should simply be copies, and then given unique labels to match their segments of the incoming bus? Is that correct?
I could do that, but it seems to entirely defeat the purpose of a hierarchical design. If I have a circuit that I want to repeat, identically, 16 times it should live in just one schematic file. This means that when I change that single file, then the change is guaranteed to be identical in all the others.
Certainly the sheets, when placed in the higher level sheet, will have unique names (so that the netlist will make sense) but the actual .sch file should be the same.
I have a work-around, but it is very clumsy… I just use segments of wire in the sheet to manually perform the mapping by applying appropriate labels. E.g
In8 ------ InDummy0
In9 ------ InDummy1
In15 ------- InDummy7
Then the InDummy[0…7] bus can connect to the 8-bit input of my 2nd sub-schematic. (In[0…7] can connect directly to the input of my 1st sub-schematic. )
It seems to work, but it is tedious for large numbers, error-prone, and very ugly.
Am I missing something, or is this a known problem/limitation/design-choice with KiCad?
How do you assign References to the components on your identical sheets? R1,R2 etc.
To have a single file, there would have to be an external database keeping track of component numbering on each of the sheets and modifying the display and printing
Well, that’s part of the point of using hierarchical design. I don’t want to have to number, and modify hundreds of resistors if I change something.
My file Amps4.sch contains 4 op-amp circuits including 12 resistors. The same schematic is used (Amps4.sch), and when a bunch of them are placed in a higher level schematic KiCad looks after the “housekeeping” of giving them unique names when the hierarchy is “flattened” into a netlist. I have 8 instances of Amps4 inside a schamtic called Amps32, so when I look at the title page inside one of these schematics it has a title of, for example
Amps32/Amps4_0 or Amps32/Amps4_1 etc etc . If I look inside these schematics I see that Amps32/Amps4_0 has (as expected) different numbers on the resistors as the equivalent components in Amps32/Amps4_1 etc.
This is all as expected.
For certain types of large designs, I think this hierarchical approach is almost essential. For example, building up a bus that’s 1024 elements wide, it is relatively compact to build it up from nested sub-schematics.
I have done this sort of hierarchical schematic generation in one other schematic capture tool, and hierarchical design is commonplace in other EDA tools.
I am just struggling to get the buses wired up in KiCad…
Doug
Exactly. A change in one hierarchical sheet is mirrored in all the hieralchical sheets with the same file name.
The bus can be splitted. But a single wire, use wire-to-bus, must arrive at each hierarchical pin. Each of these wires must have its local label. To do it fast, use the key.
I think that if you have 1024 signals, you’ll need 1024 labels at each end of the bus
I don’t know why everybody says that buses in Eeschema are only decorative. Officially the bus entry symbol are decorative only.
They have their own limited intelligence. You can join, split, label buses (Very important thing and most forgotten in some situations!) alike normal wires and pass them to the hierarchical sheets still as bus. The only problem is that the signal numbering must match because these numbers are basic property. So you can not simple split bus - even trough labelling! - to connect B[6…10] to A[1…5] in second instance. Just because the mismatching numbers.
Regarding the example give by Pedro: Yes, I know how to do that, but it is time-consuming, uses a lot of space, and just seems like a bad way to do things.
It seems to me that bus.sch should have inputs a[1…5] and split bus b[6…10] should just be able to connect to that. Obviously there would have to be certain “housekeeping” assumptions satisfied (same number of connections, incrementing numbers perhaps), but it doesn’t seem unreasonable???
Andy, I think I understand how the buses work. But now that I do, it seems to me that using the number of the signal as a basic property is rather limiting.
Maybe there can be different levels of number, or something elegant? but it seems that, for certain types of design, this is a serious problem.
We are so used to being able to program hierachically, that having the numbers in the “a[1…5]” bus being somehow fundamental, even though they are at a lower level in the hierarchy, seems just wrong. It seems to me that their actual numbers should be hidden from the higher level and there should be some sensible way to connect to them, rather like the passing of parameters by position in a function call…?
@DougM, I am passing to the same problem. I have experience with hierarchical project but couldn’t do exactly what you want.
I report this to the develop team as improvement https://bugs.launchpad.net/kicad/+bug/1730221
Yes. I’ve been getting by with a work-around. I still believe this should be improved. In my opinion this is a serious deficiency with the implementation of hierarchical sheets. We can’t yet get the full benefit of true hierarchical design.
@DougM, if you want, you can contribute in the Launchpad (the link that I posted) to the develop team check this improvement.
I agree, it was a little work around and some improvement will leave us take full advantage of the hierarchical design.
Something, in my opinion, correlated https://bugs.launchpad.net/kicad/+bug/1728248.
We don’t like re-opening old threads here. Please open a new thread, tell the problem and give a link to an old thread/post if necessary.
EDIT: bus handling has been changed in v6, you should read the eeschema (the schematic editor) manual to find out what’s new. Maybe that answers your question already.
