Splitting a bus in hierarchical schematic: problems


I’m new to KiCad, but not to hierarchical schematics.
I’ve build a schematic with a root cell containing some schematic pages, some of which contain repeated versions of other schematic pages. The repeated schematics have, as expected, the same file name but differing instance names.

I’m failing to get something to work, that seems like it should be easy… Here’s an example.

I have a bus, In[0…15] that I split and label In[0…7] and In[8…15].
Each of these labelled busses connects with a hierarchical pin on a sub-schematic called In[0…7].

So, I want In[0…7] in the top level to connect to In[0…7] in sub_schematic_0, and In[8…15] to connect to In[0…7] in sub_schematic_1…

The result is that the first one works (presumably because they have the same name), but the second one doesn’t. I’m using the import into Pcbnew to look at the netlist.

How do I do this? This must be a really common thing to do, and I’ve done things like it multiple times in other packages. How do I convince it that top level In[8…15] needs to map on to lower level In[0…7]?
(All pins are freshly imported. I’m using KiCad 4.05 for 64 bit windows.)

Thanks very much,

KiCad annotates into the schematic file.
This means that you can copy the file of repeating sheets, but each page must be given a unique file name

Thanks for the reply, but I do not understand it. It sounds like you are suggesting that the sub-sheets should simply be copies, and then given unique labels to match their segments of the incoming bus? Is that correct?

I could do that, but it seems to entirely defeat the purpose of a hierarchical design. If I have a circuit that I want to repeat, identically, 16 times it should live in just one schematic file. This means that when I change that single file, then the change is guaranteed to be identical in all the others.

Certainly the sheets, when placed in the higher level sheet, will have unique names (so that the netlist will make sense) but the actual .sch file should be the same.

I have a work-around, but it is very clumsy… I just use segments of wire in the sheet to manually perform the mapping by applying appropriate labels. E.g

In8 ------ InDummy0
In9 ------ InDummy1

In15 ------- InDummy7

Then the InDummy[0…7] bus can connect to the 8-bit input of my 2nd sub-schematic. (In[0…7] can connect directly to the input of my 1st sub-schematic. )
It seems to work, but it is tedious for large numbers, error-prone, and very ugly.

Am I missing something, or is this a known problem/limitation/design-choice with KiCad?


How do you assign References to the components on your identical sheets? R1,R2 etc.
To have a single file, there would have to be an external database keeping track of component numbering on each of the sheets and modifying the display and printing

Well, that’s part of the point of using hierarchical design. I don’t want to have to number, and modify hundreds of resistors if I change something.

My file Amps4.sch contains 4 op-amp circuits including 12 resistors. The same schematic is used (Amps4.sch), and when a bunch of them are placed in a higher level schematic KiCad looks after the “housekeeping” of giving them unique names when the hierarchy is “flattened” into a netlist. I have 8 instances of Amps4 inside a schamtic called Amps32, so when I look at the title page inside one of these schematics it has a title of, for example
Amps32/Amps4_0 or Amps32/Amps4_1 etc etc . If I look inside these schematics I see that Amps32/Amps4_0 has (as expected) different numbers on the resistors as the equivalent components in Amps32/Amps4_1 etc.
This is all as expected.

For certain types of large designs, I think this hierarchical approach is almost essential. For example, building up a bus that’s 1024 elements wide, it is relatively compact to build it up from nested sub-schematics.
I have done this sort of hierarchical schematic generation in one other schematic capture tool, and hierarchical design is commonplace in other EDA tools.

I am just struggling to get the buses wired up in KiCad…

There are some limitations regarding buses, I think this type of renaming does not work (see BUS combine over hierarchy and others).

As a workaround I think you would need to split the bus into separate members which can be reassigned correctly.

There is at least one wishlist item on the subject https://bugs.launchpad.net/kicad/+bug/1419146, whether that gets implemented or not depends on a developer taking an interest.

Exactly. A change in one hierarchical sheet is mirrored in all the hieralchical sheets with the same file name.

The bus can be splitted. But a single wire, use wire-to-bus, must arrive at each hierarchical pin. Each of these wires must have its local label. To do it fast, use the key.

I think that if you have 1024 signals, you’ll need 1024 labels at each end of the bus :sweat:

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Well, yes, in fact this schematic generates the same netlist

I don’t know why everybody says that buses in Eeschema are only decorative. Officially the bus entry symbol are decorative only.
They have their own limited intelligence. You can join, split, label buses (Very important thing and most forgotten in some situations!) alike normal wires and pass them to the hierarchical sheets still as bus. The only problem is that the signal numbering must match because these numbers are basic property. So you can not simple split bus - even trough labelling! - to connect B[6…10] to A[1…5] in second instance. Just because the mismatching numbers.

Regarding the example give by Pedro: Yes, I know how to do that, but it is time-consuming, uses a lot of space, and just seems like a bad way to do things.
It seems to me that bus.sch should have inputs a[1…5] and split bus b[6…10] should just be able to connect to that. Obviously there would have to be certain “housekeeping” assumptions satisfied (same number of connections, incrementing numbers perhaps), but it doesn’t seem unreasonable???


Andy, I think I understand how the buses work. But now that I do, it seems to me that using the number of the signal as a basic property is rather limiting.
Maybe there can be different levels of number, or something elegant? but it seems that, for certain types of design, this is a serious problem.

We are so used to being able to program hierachically, that having the numbers in the “a[1…5]” bus being somehow fundamental, even though they are at a lower level in the hierarchy, seems just wrong. It seems to me that their actual numbers should be hidden from the higher level and there should be some sensible way to connect to them, rather like the passing of parameters by position in a function call…?


I think the best and most elegant way to solve this (for now) is create separate sub-sheet to split bus.
The root sheet:

Bus splitter sheet:

Example of bus.sch:

And final result, as expected:

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Not neccessarily we want an intermediate sub-sheet.

From eeschema manual

But this solution neither solves the need of labelling of every single wire at both ends.

Sorry pal, this doesn’t work in this case. Read my first post in this topic.

Of course it doesn’t work! That’s what I meant. Even though the manual says it is the way to do it.

What DougM wants is to avoid labelling every single net, I understood.

The following schematic doesn’t either work without the individual local labels.


I like the suggestion from Keruseykaryu of building a connector sheet.

I still look upon it as a work-around, but it’s the most elegant (least bad!) one that I’ve come across.

Thanks very much,

@DougM, I am passing to the same problem. I have experience with hierarchical project but couldn’t do exactly what you want.
I report this to the develop team as improvement https://bugs.launchpad.net/kicad/+bug/1730221

I will check the solution of @pedro.

I checked @pedro’s solution, thank you. Works, but I consider this a work around and something that we could improve in KiCad.

Yes. I’ve been getting by with a work-around. I still believe this should be improved. In my opinion this is a serious deficiency with the implementation of hierarchical sheets. We can’t yet get the full benefit of true hierarchical design.


@DougM, if you want, you can contribute in the Launchpad (the link that I posted) to the develop team check this improvement.
I agree, it was a little work around and some improvement will leave us take full advantage of the hierarchical design.
Something, in my opinion, correlated https://bugs.launchpad.net/kicad/+bug/1728248.

Any news on if this works in v6?