Zones do not fill completely or at all with minimum width and clearance

Hi there,

I am having issues with zone filling when working with zones that should be minimal width and have minimal clearance to the next zone.
Basically I would like to have 3 rectangular zones with 100um width (e.g. 1mm length) and 100um spacing between them (Ground-Signal-Ground). The minimum width and clearance from the manufacturer are 100um.

If create the zones accordingly and set their clearance/width properties accordingly, the zones do not fill completely and therefore violate the min width design rule.
Sometimes I get zone fill of just 98um width instead of 100um and sometimes they do not fill at all.
I have reduced max deviation for rounding/zone fills to just 0,001, but it does not help.

The reduced fill (e.g. just 98um) might be just visual sometimes, but I also had issues with the PCB manufacturer’s DRC reporting just the 98um width.

Any ideas what I could try to make this work reliably?

Testcase here: (38.2 KB)

Many Thanks,

Kicad: 7.0.6

I raised your user level, you should be able to attach more files now.

Do you realize how small a micrometer is?

On top of that, your pictures do not mean much. They are just some colored area’s. To analyze what is going on, it’s much better if you zip up the KiCad project and post it here.

Thank you! I have updated the original post and replaced the links with embeds/attachments

I am aware (I do design integrated circuits for a living).

Of course I do not expect the manufactured PCB to be accurate to the micrometer, but the manufacturer does not accept the file, if the width in the provided kicad file is even just 1um less than 100 um.

I have migrated the previously linked zip file as an attachment of the original post

I think I can see your issue.
In the screenshot below I dragged the left GND track a bit to the right, so it clearly cuts a part of the zone in the middle:

And then, when I zoom in on the center zone, it gets a bit thinner (maybe a single micrmeter?) at the location where the knee in the left track is:

Zooming in more, with grid dots set at a micrometer:

It is as if there is some rounding error when calculating the clearance around the rounded end of a track segment. This may be some kind of KiCad bug, but I’m not sure.

In general, it’s not advisable to make your design right on the edge of what your PCB manufacturer claims to be able to manufacture. Quite often they “exaggerate a bit”, and reliability goes down when you get too close to their claimed limits. A lot of people seem to add a design margin of 20% to 30% on top of the claimed feature size of the PCB manufacturer. This also avoids the “do or do not pass” due to rounding errors and such.

Having some rounding error causing part of the problem sounds reasonable.
For curves this might even be unavoidable, but for rectangular areas with integer dimensions, this should work somehow. Maybe I will open an issue about this, unless there are some other ideas what I might be doing wrong.

I would like to avoid adding margins. The structure is needed as a landing pattern for an IC with pads with 100um pitch. With the current width/clearance, the pitch on the PCB is already 200um making bonding many pads along one chip side challenging. I could go for something like 102um width and clearance, but that would make the layout quite annoying to design.
Ultimately, I just need a PCB file with proper clearance/width I can submit to the manufacturer. If the fabricated tracks are ±20% is not that crucial (at least for the DC lines). However, at least from Eurocircuits, most of the PCBs we receive are quite accurate.

As a workaround, I have now manually drawn 100um wide tracks over the zones at the critical areas.

I’m sort of curious what others (with experience) on this forum think about this.
Should it be considered a bug?

If you need the 100um pitch, then you need it.
I’m guessing this may be something like the line drivers for LCD panels. LCD driver chips. I can quite understand why some types of “PCB” need this kind of accuracy.

I just had a look at the datasheet of an ILI9341 LCD driver, and the bumps have a pitch of 40um.

Not wishing to give you more work to answer this question . . . but did you check the Gerbers ? it might be a visual only issue and correct on the Gerbers in which case I’d consider it a small annoyance and not a 100% bug, but if the Gerbers are wrong also then I’d be more inclined to consider it a bug.

I did just now, and it’s also in the Gerbers.
First I rotated the design to get better screenshots:

Then I set the Minimum with of the zone to 0.05mm and moved the top GND track a bit, with the result:

Zooming in further on the encircled area:

And in the gerber viewer:

The displacement on the right part is on purpose because I moved the GND track, but the extra “dip” in the zone around the rounded track end is 0.5um.

In your test project, the minimum width of a zone is set to (presumably default) 0.1mm and this does not work well if you actually want features of that size.

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Another discrepancy:
When I measure the clearance in the gerber viewer, then the clearance is 500nm too big:

And the radius is half a micrometer bigger then that, so it’s a full micrometer off.

KiCad works internally with nanometer resolution, so it has plenty of resolution for this kind of work. I recall a discussion on gitlab about rotating sections of PCB which had “perfect” geometry, and caused DRC violations after a 45 degree rotation, and the fix was to add a single nanometer tolerance. So to me this suggests that rounding errors that add up to a full micrometer are probably worth a bug report to get fixed.

I’m sort of curious what others (with experience) on this forum think about this. Should it be considered a bug?

In my opinion yes. I stumbled on this some weeks ago, as this behaviour also produces many DRC-warnings from the “minimum copper connection width” warning if this check is set to the same 100um value. (the drc-warning is correct as can be seen in the many pictures - the copper is really slightly below the 100um).

But I don’t know if this can be easily be corrected - I think it’s just a result of the approximation-algorithm. Thats why I hesitated and didn’t opened a gitlab issue.
OTOH it’s better to report this - so the developers can decide themself on this topic.

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I created a gitlab issue for this on:

I trust you add your own comment to that issue for other cases where it is relevant.


Thank you very much for confirming my problem and opening an issue for this!

About the zone min width: Yes, you are right, setting it to 100um for 100um wide structures is an issue here. But probably only because of this bug, right? Ideally the zone should be fillable to 100um width and therefore fulfill the min width requirement.

I will continue to watch the Gitlab issue

While I agree that this behavior isn’t desirable, I want to caution that it may be very challenging to fix without introducing other problems, and so it may be decided to be out of scope (others will make that call).

In other words: it might be good to think about other ways to achieve your design goals, in case there isn’t a fast fix.

Thank you, I understand.

Ultimately, I would prefer to avoid using zones for these structures anyways and rather draw polygons on copper layers (as far as I understand that is not possible to implement in KiCad due to restriction of Gerber format?).

Anyways, my workaround is to manually draw 100um wide wires on top of the zone at the crucial segments. Luckily the minimum with segments of my zone are straight/rectangular segments.

You can have filled polygons on copper layers . . .


. . . just don’t think they can be on a Net which might cause you other issues.

Ah, right, I forgot. Since, you cannot assign a net to them they felt useless to me and I ignored them. I will double-check if DRC still detects proper connectivity. Edit: It does not

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It’s possible, and something we’d like to do in the future sometime. It is not limited by Gerber.

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