Could be, I’m not familiar with KiCad’s internals to have a strong opinion about this. However, currently there seems to be some arbitrary rounding to 500nm and that seems rather large compared to KiCad’s internal resolution.
Combine that with a bump pitch of 40um of the ILI9341, which requires 20um tracks and 20um clearance, and it seems that it’s at least looking into whether it’s some arbitrary set tolerance or not.
@maxanier For you, the simplest workaround is to set your design rules to 90um or so, while keeping your grid at 100um. I am aware that this conflicts with your current PCB manufacturer’s rules.
I also wonder why you use zones at all for those thin sections. It is what tracks are designed for, and as you already noticed, these do keep their width. We also may come up with a different solution if we see more of your design. Currently it’s just the very simplified example project.
I am designing a “breakout” PCB for two RX/TX ICs. Several DC supplies have to be routed and some mm-wave signals require transmission line structures. I created the transmission line structure in Keysight ADS and imported in KiCad via DXF. Therefore, they are all polygon pours. Some parts are not rectangular, so they require polygons anyways.
However, it is not that big of a problem (at least for this specific design), because I can quickly manually place wires at the crucial segments. So I can continue using KiCad for this layout. It would still be nice, though, if the zones would fill properly (or there were would be solid polygons).
One workaround that may or may not help you is: you can create solid polygons that have nets inside footprints (as custom-shape pads). So, for the portion of your design that is fanout from the actual footprint, if you have transmission line shapes to import exactly, you could actually make those part of your footprint if you wanted.
Craftyjon’s suggesion may work.
I have seen it quite a lot of times that adding graphic shapes to footprints is abused to add special features.
Sometimes you just want copper zones defined by their outlines, and no frills or auto clearance outline generations. I wonder how useful it would be if KiCad had a function to do that. Maybe “upgrade” a graphic polygon on a copper layer with a net name, or maybe to just disable the outline clearance generation from a normal copper zone, so it’s always generated as drawn by the user.
DRC would then preferably still flag violations, but leave it to the user to fix them.
This would also be quite similar to painting an area with locked tracks.
Edit: @craftyjon Oops. It’s not my brightest day. I did give #4809 an upvote though.
