I am working on a 4-layer board and would like to view the inner layers and the vias to make sure the vias are connected correctly. However, I am only able to see the top and bottom layers of the board in the 3D viewer:
(My board is a little unique: the two inner layers are just large ground pours, both for electrical connection but also for heat spreading. But I would still expect them to be visible in the 3d viewer.)
A previous thread on this topic from 2018 said that you could see the inner layers and vias if you disable “Show board body” and “Realistic mode.” However, I have done both of these things already and do not see the inner layers. I do see the one via, as shown in the image above.
The screenshot in the thread you link to is not from KiCad. Apparently it is from “zofzpcb”.
You can see inner layers, I’ve done so several times and also posted screenshot here with the via tubes visible. The hint to disable “Realistic Mode” is not true. I think it only changes colors.
I can not see what you did from a screenshot. I suggest you start with: 3D viewer / Preferences / Reset to Default
And after that only disable the things that are really in the way.
Those things are in: 3D Viewer / Preferences / Preferences / 3D Viewer / General
Maybe you also turned off Show Filled areas in zones, but if your inner layer are only a zone, then it’s logical you don’t see it if you turn it off.
I do wonder where the via’s are. Are there any via’s on your PCB?
Below a screenshot from KiCad’s 3D viewer with the settings from above. You can see the via’s through the PCB.
I just tried this and I do not see inner layers either. Is there a pref to enable them somewhere? This is a 4-layer board and no inners. I don’t think it is just an unfilled zone issue as I would still expect inner pads at via/pth tubes.
I don’t think it is just an unfilled zone issue as I would still expect inner pads at via/pth tubes.
Not always. Since V6, KiCad has a partial pad stack implementation and inner pads for vias can be turned off for layer which have no tracks or zones connected. You can do this on a pad for bad basis, by selecting a single pad, depress e to edit it’s properties, and then edit the “copper layers”
The screenshot below is from the Olinuxino A64 Rev C (which is freely available on Github) It is a 6 layer PCB and I turned the annular rings off for a single pad:
It’s a bit annoying, I can set the annular rings for single pads, but I can not find a way to do it for the whole PCB or even a whole footprint (on the PCB) with a few mouse clicks. Changing individual pads is madness.
Well, that is interesting. Not sure the pros and cons of turning off internal pads that have no connection. Not having unused internal pads is perhaps a better impedance for high freqs and sharp edges (since they would be little stubs)? I don’t work that high on the spectrum.
But I still cannot see inner copper in the 3d viewer on a 4-layer board. Dunno how your 6-layer board is showing that.
I don’t no if there are disadvantages for removing these rings, but it does have clear advantages.
Less capacitance.
Less reflections from the rings. (for high frequency content signals).
Planes on inner layers can have smaller disrutions.
More room for tracks on inner layers.
Back to topic:
Do you have any copper tracks on inner layers, or only zones?
If you draw tracks on inner layers, can you see them?
You can download the Olinuxino A64 from github and open it. How does it look on your side?
Or create a small test project for a 4 or more layer PCB. Then you can post it here and we can compare differences and settings.
My understanding is that there are manufacturing and reliability concerns associated with removing inner annular rings. How important they are depends on many factors, as usual.
Do you have any info t back that up?
I am not aware of such (potential) problems. Only thing I can think of is that the clearance may have to be a bit bigger because of tolerances of the drill placement, (different process steps) while copper to copper (on the foil, not to the via tube) clearance is a single process step, and tolerances can be controlled better.
Honestly, I don’t have a lot of info on this. Mostly feedback from customers who are worried about thermal cycling. I do primarily power PCBs, so temperature excursions are often amplified.
Your question did prompt me to revisit this, and as a result I will try removing internal annual rings for some designs where the transitions are much faster than typical power designs. I’m less worried about the via impedance, but it allows me to get more copper in some locations where more is better.
