Vias cutting GND plane

[Spaceboy]

Hello,
Which is better: two vias bunched together or separated with a bit of gap in between them for a better ground plane?
Thank you

[Piotr]

The smallest gaps in GND the better.
If GND is at internal layers than removing from via unused pads will allow GND zone to go even between these two vias that are close to each other.

[paulvdh]

@Piotr

The smallest gaps in GND the better.

Overall, yes, but it is not always important.
The main usage of the GND plane is to reduce the loop inductance of all tracks. Loop inductance is dominating for frequency content over a few kHz, and then the return current will follow the track in the GND plane. As a result, the GND plane must be under all tracks. And also, as long as there are no tracks going over the gaps in the GND plane, it does not matter much when there are some bigger gaps.

[Piotr]

@paulvdh

Overall, yes, but it is not always important.

I’m not familiar with high frequency. In my opinion you never know when it is important or not. The immunity of all devices to fields up to 6GHz is tested. It is because cell-phones are now everywhere.
3E8/6E9 = 5cm.
Each hole in GND is slot antenna. I have no knowledge about such antennas, but from articles I linked here long time ago:

Decoupling capacitor via placement

I didn’t read that book but I suppose you can replace it with: I think it is enough for most pcb designers.

I remember that opening in shield being 1/10 of wavelength (so 5mm for 6GHz) ruins shielding efficiency quite well. How with such opening in PCB GND. I have no knowledge and no tools to analyse it so I just prefer to not have bigger holes than are absolutely needed.

[Spaceboy]

@Piotr

than removing from via unused pads will allow GND zone to go even between these two vias that are close to each other.

Hey, thanks for the response but I didn’t understand what you meant here.

Also, this board is for a cubesat on board computer with an STM32. It contains SPI and I2C, RS422, RS485, CAN and UART

Thanks

[Spaceboy]

@paulvdh

The main usage of the GND plane is to reduce the loop inductance of all tracks. Loop inductance is dominating for frequency content over a few kHz

Adding to my question, if my stackup is having signal layers as the outer layers, I guess it is better to pour then with gnd copper to isolate things like SPI lines. So what is your suggestion on where all to place sticking vias? Like every point artifact that might become an antenna? Thanks

[Piotr]

@Spaceboy

@Piotr

than removing from via unused pads will allow GND zone to go even between these two vias that are close to each other.

Hey, thanks for the response but I didn’t understand what you meant here.

Try Tools - Remove Unused Pads…, check Vias and then Remove…
Then refill zones.

[davidsrsb]

My opinion answering the OP question is that for high frequencies, a mesh is better than a slot, so avoid putting vias too close

[paulvdh]

@Spaceboy

Adding to my question, if my stackup is having signal layers as the outer layers, I guess it is better to pour then with gnd copper to isolate things like SPI lines.

No. Once you have a GND plane (or even GND planes on multiple internal layers), adding more GND in sections of the outer layers does not help much for EMI anymore. It can help for lowering DC resistance on PCB’s with very high currents.

[mousey]

A long run of vias close together making a clear cut thru the ground plane is not a good idea, the two that are spaced apart are fine. You could pepper the board with a few of such pairs and it wont make any difference. When you start using higher frequency than what you have stated, then it’s time to hit the books To be honest you’re just trying to limit the amount of holes in the pour as much as you can ! with a dash of common sense and experience ( that will come) you will be fine. It was a great question

[Spaceboy]

Oh okay, so having a ground pour between SPI lines will not do much to limit crosstalk as just spersting them by maybe twice the trace width without ground pour in between?
I also guess it’ll be better if I remove copper islands or stitch them to ground right?
Thanks

[Piotr]

@Spaceboy

do much to limit crosstalk as just spersting them by maybe twice the trace width

When (10+ years ago) I was searching for crosstalk I remember that practical rule I found was to have distance between tracks being 3 times track width. But it is ‘internet knowledge’.
My problem was (it was not SPI) that I wanted to filter out (at shield border) high frequency from tracks so used small capacitors just out of shield and 1k resistors just in shield. That way I had incoming line driven by 1k going paralel to line driven directly by IC output (its 1k was at its end).

[paulvdh]

One way to limit crosstalk is to increase the distance between parallel tracks, but this needs extra PCB area. Once the distance between tracks is so big that you could put a GND track in between, crosstalk probably is not a big issue anymore anyway. Tight coupling with the GND plane under the track (a layer of prepreg is around 0.1mm) also reduces the external field, and thus crosstalk.

Another way to limit crosstalk is to change the order of the signals every now and then. In digital systems, quite some noise and crosstalk can be tolerated, but you have to keep it under certain levels. So all signals (for example a databus) having some crosstalk with each other is OK, but running two of those close to each other over the whole PCB may exceed the acceptable limit and wreck your circuit.

[Spaceboy]

Seems like I have a bit of research to do

[RalphBSz]

You probably have frequencies of up to ~MHz on your board, with SPI and I2C being the fastest ones. At those frequencies, you don’t have to be super careful. We used to wire-wrap boards at these frequencies with TTL and CMOS logic, and it worked. With the small PC boards and good design rules today, I think a bigger concern is currents, and the voltage shifts they create: If a chip has only one ground or Vcc pin, and that pin is connected with only a 4" long trace that’s 6 mil wide, the poor chip’s power supply is going to be bouncing a lot. In theory, having both a ground and a power plane (4-layer board) should help. But with today’s systems often having multiple supply voltages, and a high density of signal wires, things don’t always work out perfectly.

Note: I’m not saying that you shouldn’t move those two vias apart to restore the ground plane between them: you absolutely should (if easy), since it can only help. I’m only saying that other issues may be more important.

[hermit]

@RalphBSz

and good design rules today,

One reason I kinda believe that people shouldn’t abandon ‘best practices’. You don’t know what bites you until it does. And most of us don’t have the means to test some bizarre failure that could occur. Too much bad content out there generating revenue by ‘disproving myths’. I’ve seen some (deleted) out there that can be picked apart by your average rock, if the average rock cared enough.

[Sudzy]

I am not sure of the technical level here, but a good book on this subject was written a while ago. It is “High Speed Digital Design : A Handbook of Black Magic” by Howard Johnson and Martin Graham. They do a good presentation about PCB design and the concerns about EMC; both the radiated and intercepted sides. They used as little math as possible to explain what goes on with high speed digital signals and how to reduce the impacts of the design.