I hereby certify that I am not simply asking someone else to design a footprint for me.
This is an auto-generated message that is in place on the “footprints” section of the KiCad.info forum. If I remove it and ask for a footprint to be designed anyway, I understand that I will be subject to forum members telling me to go design my own footprint or referring me to a 3rd party footprint site.
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[V6.0.1-0]
I am looking for a better way to create a via which, when connected to a power-plane net with a surface trace, does not connect to that power-plane when it passes through the board.
I believe I can do this by manually adding a keepout circle on the power-plane layer in question, concentric with the via. I don’t know of a way to group the via and the keepout, so this method requires manually managing the location and alignments of the via and keepout for all such vias. Much more friendly if the via could just be built this way as an entity.
Is there another way to do this in KiCad V6?
Any plans to add a via editor to KiCad in the future?
I don’t think there is a work around for vias as such, but it should be possible for pads: add TH pad (with supersmall annular ring), and place smd pads over it on top and bottom layers (true annular rings). This pad(via) will be like unit. This does not have any practical use, because you would need to add these “vias” to schematic, and also, it seems, that vias looks different in gerbers and requires less precision from manufacturer: (V6) Via Instead of PlatedThoughHole? - #3 by Frederik
The currently-planned padstacks feature does not include this feature (keepout on a certain layer). Please open a feature request for it so we don’t forget about it.
It’s kind of like a net-tie situation, where you have one net that you want to treat as two nets. For example if you have a feedback trace for a power supply, and you want to route that feedback trace to the other side of the board but not connect it to the power plane that is fed by that power supply (because you want to take feedback from a specific part and account for the voltage drop through the PDN)
My use of such a feature is for bypass capacitors in certain instances. With a bypass cap on the back side, the non-grounded end of the cap gets two vias, usually on opposite sides of the capacitor pad. The first via feeds the cap from the power plane, say from the left side, and the second via, say to the right side, supplies power through to the top side to the IC power pin. The idea is to lower the effective inductance of the bypass cap as much as possible from the perspective of filtering the power plane for the IC. The tradeoff is greater inductance from the cap to the powered IC, since the cap is further away than the power plane where the second via connection has been defeated. But the length of the capacitor is very short to the power/current on its way to the IC. Basically, feed the cap from the plane, and feed the IC power pin from the cap.
I’ve done this in a number of board layouts in the past, but I was always working with a layout designer, and I don’t really know what they did in the PCB tools to make this work. Here I’m doing my own layout.
As I mentioned, and just tried again, I believe I can draw a keepout polygon (not a circle directly that I can find) on the power plane layer in question concentric with the via, selecting to keep out pours and traces, to get this functionality. Then I have to manage the relationship between the keepout and the via manually. For this board, I probably won’t employ the workaround, as I don’t need the special bypass routing feature bad enough to take on the complexity.
