I’m creating a 4-layer pcb with some ‘high current’ traces. These traces go to 2 amps max. but they need via’s to go from from surface mounted components (top layer: mini relais and mini fuse holder) to hole mounted terminal blocks (bottom layer)
I’ve used the KiCad calculator with the standard 0,4mm finished hole diameter and a 0,035mm plating thickness. This gives me a max. current of aprox. 3 amps.
In the board setup of the pcb editor (just getting started, never used it before) i’ve imported all the netclasses from the schematic editor and assigned the netclasses to the nets.
I’m strugling to assign the via hole size and the via size in this board setup.
Can i assume that the the copper thickness in the via; with via size 0,6 mm and via hole 0,4mm; is 0,2mm??
That seems a lot because the default plating in the via with the calculator is only 0,035mm.
Or am i interpreting everything wrong?
Additional question about this topic:
The pcb manufacturer Next PCB can estimate the price for the pcb and there i can choose the different options (i’ll leave most of them default). The only choice about is vias is ‘Via Processing’ (i’ll choose Tented vias).
The option ‘Min. Drill Hole’; is this the minimum hole diameter for the thru-hole components? Or is this also a minimum hole diameter for the vias? I assume that the minimum via diameter will affect the price but i can’t seem to find it specifically in the Next PCB option list.
Standard thickness for tracks is 35um (I.e 0.035mm) but 17um is also fairly common, especially for the inner layers, so make sure you order the layer thicknesses that you want.
Normally via plating is around 17um. The way that PCB production works, is that the base material normally has a 17um copper thickness. Then drilling all the (plated) holes is one of the first steps. After the holes are drilled, the inside is made slightly conductive, and then the whole PCB is dunked into an electrolysis bath, and everything on the PCB gets extra copper. So the existing copper goes from 17um to 35um, and the holes of the via’s go from 9um to 17um.
For more details, there are some very nice video’s on youtube about video tours inside PCB factories which explain the whole process in more detail.
thx for this practical info! I’ll do a little more digging because if the 17um is the standard then i need larger vias for those higher current traces. If nextpcb doesn’t support these larger vias i need to come up with a other solution.
Still don’t know if in the pcb editor-pcb properties-netclass the difference between the via hole and the via size is the thickness of the plating in the via.
It has absolutely nothing to plating thickness.
Vias are like THT pads. Do for THT pads you expect that they have copper according to their size going through whole PC from top to bottom?
The “via size” is the outer diameter of the via, and this must be bigger then the via itself to make sure there is still an “annular ring” around the via hole. This “minimum annular width” in the board setup is by default set to 0.1mm (Which I think is a bit smallish, because of PCB production tolerances).
The Via Hole is almost always interpreted as the inside diameter of the finished hole. The PCB manufacturer generally uses a bigger drill, depending on the plating thickness they use. In practice, it usually does not matter much for via’s because the difference is small, but for THT pads (Especially press fit connectors) the difference can be important.
On Windows, the Saturn PCB Toolkit is the goto tool for things like via current rating https://saturnpcb.com/saturn-pcb-toolkit/
On high current traces I use several vias in parallel to get the required rating with a safety margin - via plating is not a well controlled process.
Now i’m getting somewhere! thx!
For now i know how large the vias (via hole and via size) need to be thanks to the combined info of you and :
and:
The external 2 amp traces are 1mm (35µm) so they have a safety margin (up to 2,4 amps). That means i can set a fairly large via hole of 0,8mm and a via size up to that 1mm (so the ring is aprox. 0,2mm, hopefully large enough to guide the 2 amps from the trace to the via). The Kicad calculator says with a drilled hole of 0,8mm and 17µm plating i can go up to 2,8 amps.
Thx guys for the info!
little off topic: I’ve checked the distances and sizes of holes and copper zones around the thru-holes of the terminator pins (pin diam.1mm, hole 1,6mm !!?? so says the downloaded mod-file). I’m gonna check out the copper zones and distances of the surface mounted mini relais’ to because the 2 amp must be approved for 230VAC so the distances are important to.
My local manufacturer not accepts so small annular width (0.15 is minimum).
You should all the time have in mind that hole can be made not exactly centered in via so it can happen that the width you assume is reduced just at the side the current is flowing.
Adding teardrops to vias helps increase the yield if there is a registration accuracy issue since there is a larger area that needs to be hit due to a non precise drill bit to cut the track.
Yeah, thx for the heads-up! …at first i thought that this was a ‘drop’ of solder but now i see it’s actually a extra copper zone to make the connection between pad or via more reliable.
That would be an annular ring of 0.2mm and that is usually sufficient. But to be sure, it’s always best to check this with the PCB manufacturer that is going to make your PCB’s. They are not all the same. In your opening post you also mentioned:
Multi layer PCB’s often have a higher resolution then the 2-layer pooling services, so your 200um annular ring is likely plenty.
And yes, teardrops are a reliability improvement. both against drilling misalignment, and against track breakage in highly stressed area’s (such as PC104 connectors)
For higher currents I do not use vias at all.
I place something like a “measurement point”.
During production these are filled with solder and you do not have to worry about 35um.
KiCad calls it a “testpoint”, and it has both symbols and footprints for them. “TestPoint_Small” is just a small round circle in the schematic, and the least intrusive. For DIY it’s easy to put a dab of solder on them, for automated production you can adjust the amount of paste with the aperture size on the paste layer. Note that it’s perfectly fine to to make the aperture pad on the paste layer bigger then the pad. When the solder melts, it will still all wick into onto the pad and into the hole.
But how must this testpoint be applied? I have creating a pcb with mainly surface mounted part on the top layer the inner layers are the +5V plain and the GND plain.
The bottom layer is a routing layer where the thru-hole terminators are soldered.
So the high current stracks start on the top layer and need to get to the bottom layer.
These testpoints need to be applied in the schematic editor but can they replace the vias in the pcb editor? Do these testpoints make a connection from top to bottom layer?
Or do i need to place the testpoints on the vias itself? …and what do i need to add to the pcb design if i want the manufacturer to apply a drop of solder on the test point or via?
