KiCad has both schematic symbols and PCB footprints for test points. And you can easily modify them yourself too. Being able to modify symbols and footprints are essential skills anyway.
If the footprint for a testpoint is an THT pad, then you can connect tracks to it on whatever layer you prefer. It’s just a normal part of the net just like all other pins of all your footprints.
A THT pad combined with an aperture pad on the solder paste layer would be enough. The hole size of the THT pad must be quite small, or else the solder will just drip out of the bottom, and you’d have to balance the amount of solder paste with the hole size. Solder paste will already be pushed into the hole during stenciling. I don’t have the experience to know how that would really work out or what the limits are. I guess that a hole of 300um to 400um would be a good start.
Frame challenge on that little bit by itself: Through-hole parts are available on every layer. Why not just run a trace directly to them? No vias at all.
A single-layer process (of course) only has things on one layer, which is usually visible while soldering through-hole parts, and thus on the bottom. If you’re used to making your own PCB’s at home, or if you’re coming from a mass-manufacturing job where a second layer does cost extra (so you use a TON of through-hole jumpers and still come out cheaper than a second layer…), then it’s understandable to get into the mindset of, “Through-hole parts connect on the bottom.”
But they don’t have to. All through-hole pads are effectively their own vias already. So any layer works just fine, and there’s really no point in changing layers just to connect to a through-hole part. Just stick a track to the pad on whatever layer it happens to be, and call it good.
I haven’t yet used internal layers for signals (good for intellectual property protection, I guess, or to escape a BGA or other dense footprint, but a troubleshooting nightmare), but that would work just as well too…