I have a component simulation model that is specified in Verilog-A, which I would like to include into a simulation in KiCad. Is that supported?
In the user manual of ngspice (I am no expert) I see this should be possible. However, in the “simulation model editor” of KiCad it does not seem to be a supported format:
If I blindly proceed and put the file there, KiCad shows this and crashes:
Any help is appreciated.
ngspice supports using Verilog-A compact device models for simulation.
Please see chapter 9 of the ngspice-43 manual (chapter 13 in version 42). This probably has never been tested with KiCad.
Of course this does not mean that it cannot be done!
May I suggest the following approach:
Firstly confirm that your Verilog-A model can be compiled by OpenVAF (https://openvaf.semimod.de/) into a shared library (MS Windows, Linux are o.k., macOS is not supported). You may call it mydevice.osdi for example. The compilation success is inevitable for the following actions!
An Eeschema symbol for the new device is required.
Create a subcircuit model for the new device:
.subckt newdev n1 n2 n3 n4
N1 n1 n2 n3 n4 newmod instp1 instp2
.model newmod va-module-name mpar1 mpar2 mpar3
.ends
n1 n2 … are the device nodes
instp1 instp2 … are the device instance parameters, as defined by the VA model code.
mpar1 mpar2 … are the device model parameters, as defined by the VA model code.
Put the subcircuit into a file and attach it to the symbol in the usual way.
Create a file named .spiceinit (leading dot required!). Its location depends on the OS (see ngspice manual 12.6 for ngspice-43 or 16.6 for older versions). Write the code to load the newly created shared library into this file:
osdi <path>/mydevice.osdi
Hopefully that’s it! I have not tested this approach, but it sounds reasonable.
Thank you for your guidance, @holger , it is very much appreciated. Unfortunately OpenVAF is not compiling my model, it crashes without any meaningful error message. I opened an issue in their GitHub.
I will see if I find another solution, or just try to translate the Verilog-A model into a Spice model (which I don’t know if it is possible, I am not very much into these technologies).
UNfortunately, since Pascal Kuthe has left the project, it may be difficult to obtain an answer.
This is what I get when compiling rram_v_1_0_0.va:
error: unexpected token ','; expected ':'
--> \\?\D:\Spice_general\OpenVAF\10_4231_D37H1DN48\rram_v_1_0_0.va:59:46
|
59 | parameter integer model_switch = 0 from[0, 1];
| ^ expected ':'
error: unexpected token ','; expected ')'
--> \\?\D:\Spice_general\OpenVAF\10_4231_D37H1DN48\rram_v_1_0_0.va:74:40
|
74 | parameter real T_crit = 450 from(390, 460);
| ^
| |
| expected ')'
| unexpected token
error: unexpected token ','; expected ':'
--> \\?\D:\Spice_general\OpenVAF\10_4231_D37H1DN48\rram_v_1_0_0.va:76:49
|
76 | parameter real deltaGap0 = 0.02 from[0, 0.1);
| ^ expected ':'
error: unexpected token ','; expected ')'
--> \\?\D:\Spice_general\OpenVAF\10_4231_D37H1DN48\rram_v_1_0_0.va:78:40
|
78 | parameter real T_smth = 500 from(400, 600);// activation energy for vacancy ge
neration
| ^
| |
| expected ')'
| unexpected token
error: unexpected token ','; expected ')'
--> \\?\D:\Spice_general\OpenVAF\10_4231_D37H1DN48\rram_v_1_0_0.va:97:48
|
97 | parameter integer rand_seed_ini = 0 from(-1.6e9, 1.6e9);
| ^
| |
| expected ')'
| unexpected token
error: unexpected token ','; expected ')'
--> \\?\D:\Spice_general\OpenVAF\10_4231_D37H1DN48\rram_v_1_0_0.va:99:44
|
99 | parameter real time_step = 1e-9 from(1e-15, 1);
| ^
| |
| expected ')'
| unexpected token
error: function 'rdist_normal' is currently not supported by OpenVAF
--> \\?\D:\Spice_general\OpenVAF\10_4231_D37H1DN48\rram_v_1_0_0.va:146:20
|
146 | gap_random_ddt = $rdist_normal(rand_seed, 0, 1) * deltaGap / (1 + exp((T_crit - T_cur)
/T_smth));
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ unsupported function
|
= This function is part of the Verilog-A standard but currently not implemented by OpenVAF
If this function is important to your application, create an issue:
https://github.com/pascalkuthe/openvaf/issues/new
error: could not compile `rram_v_1_0_0.va` due to 7 previous errors
done
Replacing the offending ‘,’ by ‘:’, this one is left:
$ ./openvaf-compile-va-10_.sh
error: function 'rdist_normal' is currently not supported by OpenVAF
--> \\?\D:\Spice_general\OpenVAF\10_4231_D37H1DN48\rram_v_1_0_0_mod.va:146:20
|
146 | gap_random_ddt = $rdist_normal(rand_seed, 0, 1) * deltaGap / (1 + exp((T_crit - T_cur)
/T_smth));
| ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ unsupported function
|
= This function is part of the Verilog-A standard but currently not implemented by OpenVAF
If this function is important to your application, create an issue:
https://github.com/pascalkuthe/openvaf/issues/new
error: could not compile `rram_v_1_0_0_mod.va` due to 1 previous errors
done
Maybe you can refine your issue at GitHub.
I once have made a memristor model available in ngspice (two versions, not much tested).
See ngspice / ngspice / [2af390] /examples/memristor for simple circuits and
ngspice / ngspice / [2af390] /src/xspice/icm/xtradev/memristor for the code model.
These may serve as templates for your own or the Stanford model.
B.t.w. my OpenVAF version from Downloads | OpenVAF
Indeed I fixed all the syntax errors, and the $rdist_normal I just removed it completely, i.e. replaced $rdist_normal(...) by 0. After that I just get OpenVAF encountered a problem and has crashed! and no more information (more details in the GitHub issue).
About the memristor models for ngspice, thanks a lot! I was already experimenting with them a few days ago and for sure will use them as a starting point.
I am using OpenVAF for Linux.
@holger may I ask you a question about your memristor model? In line 28 of memristor.sp you added a DC voltage source with 0 V in between the current source and the capacitor, instead of a cable. Why? Is this related to some computational reason? I tried removing it and I saw a small change in the behavior.
To be honest, I do not remember. Perhaps I thought to monitor the current in this branch.
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