I’m new to PCB design and trying to understand the via manufacturing process. I came across this article: Via Covering Process—Using the Correct One in PCB Prototype, which explains different types of via covering processes like Tenting Vias, Vias Not Covered, Resin Plug-hole, and Plugged Vias.
I’m currently designing a small two-layer PCB and trying to figure out what type of via coverings I should use. IPC-4761 Specifies 7 Different Types of Vias, but I’m a bit confused about how to choose the right via for my design.
How do I determine the best via covering process for a basic two-layer PCB? Also, should I be worried about via current carrying capacity for power traces?
Thanks for your response. For my design, I have some critical traces running near vias, and I’m concerned about potential solder mask clearance issues if I leave them exposed. On the other hand, if I tent them, I worry about trapped chemicals or reliability concerns during assembly.
In your experience, have you encountered cases where tenting vias caused issues in manufacturing or assembly? Also, for power traces, is there a general threshold where plugged vias become necessary to prevent reliability issues?
I think via covering process may be a subject for technologist at a PCB production plant. For me designing PCB via was always simply via and I never thought about it deeply.
I assume that if at PCB copper is initially 18um and during plating rises to 35um than I assume via plating at the same time rises from 0 to 17…18um. I suppose (but I’m not sure) that if plating is made electrochemically than in center of hole plating can be thinner.
For power traces I simply add more vias to get more copper “through” the PCB . . . and I go a little over the top to be safe. If you need more current and are short of space use smaller holes, but smaller holes give you less area through the hole . . . in general I favour “larger” holes.
Can you name a serious PCB manufacturer that offers IPC-4761 compliant tented vias as standard? I don’t even know of a manufacturer that still offers the dry film resist (required by IPC-4761) as “standard”.
Even those that do offer dry film resist (on special request) recommend avoiding tenting.
Although many designers submit manufacturing data with “tented” vias, and although many PCB manufacturers don’t argue with their customers, this method is wrong.
The via barrel shall be open when the copper finish (ENIG, HAL etc) is applied to remove residues from previous process steps. Maybe filled and capped vias are an exception to this rule, but if you order these, you don’t need to worry about it anyway.
If you need to close your vias because you are using vacuum fixtures, you should plug them.
If you need small distances between vias and pads, you should uncover just the via hole, so the edge of the annular ring is still covered, but the hole is open. Find a photo here:
JLCPCB also writes “We use LPI (Liquid Photo Imageable) solder mask”, therefore this kind of tenting is not IPC compliant. They simply don’t care if customers provide bad data (like many other manufacturers).
To be clear: You will not exhibit tons of failures if you smear your via barrels with solder mask. The increase in failure rate caused by “tented” depends on the PCB manufacturing process and the environmental conditions.
