Hi everyone,
I got a big issue on Kicad today.
A guy in my team draw a board and we produce it to do some tests. I got it on my desk now and it’s not working because 5V signals are not ok.
So I open it on my kicad and highlight the complete 5V signal :
As you can see there is 4 separate groups of 5V but they should be connected together and no unconnected nets appears!
If I try to route a 5V wire between 2 groups I can connect them but kicad doesn’t print any unconnected connection at all.
From the screenshot i can not really tell a lot.
Might there be a connection on a layer that is not pictured? (Some vias currently look like the go to nowhere.)
This board only have 2 layers and there are all displayed here.
As you can see in the picture Kicad highlight both layers, I check many times all the 5V wire are displayed, there is no connection between 5V groups.
Lonely vias link ground copper planes between layers.
Might you be willing to share the pcb file. (You can send it to me via private message.)
I would take a look at it.
What does DRC say?
Also, what version are you using? I think there were some bugs in the OpenGL canvas regarding unconnected nets.
But not in this direction. There is a bug where the unconnected count is non zero but everything is connected according to DRC.
It’s too early to rule anything in or out. It’s not clear what “this direction” is yet. There are multiple things that could lead to this problem, we need more data.
@Rene_Poschl I can’t Send you any PM I don’t have sufficient point in this discours I think.
I run The DRC twice the first one I got an unconnected number to 15 but nothing printed in the list the second time Errors appears.
But this process don’t update the unrouted signal, but it show me other similar issue on another signal.
I sent you a pm. You should be able to answer to it. (To get higher rank simply read a few posts in different topics, maybe give a few likes to people who you think deserve it.)
You need to first run drc then press the list unconnected button. (It is important that you run DRC first. otherwise list unconnected uses old connection data. In kicad DRC does more than simply check the board. It is responsible to generate the connectivity data.)
Thank’s to @Rene_Poschl I understand my problem.
DRC display errors and I just hide ratsnet, That’s why I can’t see unconnected signals…
To resume this is a noob fail.
A bit more details from my understanding of our private conversations. (Might be a learning experience for others.)
It seems @Metabolik (or someone on the team) send the files to a manufacturer without running DRC first. They thought it is enough if they no longer see any ratsnets. (But they turned of the visibility of ratsnets.)
Maybe they also thought that there can not be a DRC violation because they used the interactive router. (Sometimes the interactive router does place stuff where DRC later complains.)
When i ran DRC on his project i got quite a few trace near pad and via near trace errors as well as a lot of unconnected pads (affected nets where +5V, GND and even Reset). So kicad did find the unconnected +5V islands.
In short: Run DRC and use the list unconnected function provided by DRC to ensure everything is ok. Never ignore DRC errors.
DRC also fills the zones. Is there any other way to fill zones based on the current tracks?
What do you mean with “based on the current track”?
In open GL:
Filling all zones can be done using the Hotkey “B” (For a list of all available hotkeys press shift+?)
Filling specific zones can be done by rightclicking on the zone outline -> Zones -> fill zone.
“based on current track” just means based on the current layout, if you’ve moved tracks since the previous fill zones.
Thanks for the notes on how to fill zones outside of DRC!
I’ve just encountered this problem and it’s led to me getting five boards made with a mistake on them. (Luckily it’s fixable on this design.)
Running DRC shows no errors, “List unconnected” doesn’t report anything wrong, and no rat lines appear, however there’s a single pad which is only connected to a stub of track, not to the rest of its net.
The entry for this net in the netlist looks fine, and I’ve tried re-reading the netlist and even using the “Rebuild board connectivity” button, and still the problem persists.
I’m using KiCad version 5.0.2+dfsg1-1~bpo9+1. I’m happy to share the files if anyone wants to take a look. It certainly looks like a serious bug to me, but it could be that I’m doing something wrong.
Anyone interested in taking a look?
It is a three year old thread. Version 5.0 is not supported anymore. Update to V5.1.6 and see if the problem remains.
The least you should provide is a screenshot of the pcb area in question and part of the schematic that shows how it should be.
OK. Here’s the affected region of the PCB, with the questionable net selected:
Notice that the left hand trace doesn’t quite connect to the round pad at the top.
Here’s the schematic, with the affected net highlighted:
The relevant bit from the netlist:
(net (code 19) (name /ECI_SS)
(node (ref J1) (pin 12))
(node (ref R8) (pin 2))
(node (ref U4) (pin 11)))Upgrading to the latest version means upgrading the Linux distribution on this machine; I’ve set this going, but it’ll take a while. I’ll follow up when it’s done.
It would be easier to check if you would give the whole project (zipped) or at least the .kicad_pcb file here.
Ah, OK, I didn’t realise I could attach non-images. Hopefully this is enough - let me know if you want to see anything else.
drc.zip (33.4 KB)