Two track failing to join

Layout
1

Dear all

I found a strange issue when i try to join 2 different track width one of 0.12mm and another of 0.3mm they never join why

Regards
Nick

2

not had problems like that yet in any version… are they on the same net?
Is there something in the vicinity that doesn’t allow the thicker track to ‘lay down’ due to clearance?

See routing help options:

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3

Dear Kicad

so far i have done a bit of routing wanted somebody to have a look at it and review the routing

routing is done only for the part circled in red bellow is the schematics attached

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  • I would like somebody to review the routing and let me know it is as per the schematic mentioned in the attached png file

  • In the kicad_pcb file i wanted to know how do i connect to ground from top and bottom layer.

  • Is it better to connect all ground point in the circuit to the ground plain through a via at various place. or connect all ground points using track and then finally connect one point in the entire front.cu to the ground plane. i feel first idea is better as it avoids lot many tracks being built up. let me know your feedback

Regards
Nick

6

this is a 6 layer board stack up is as follow

front.cu
ground.cu
rout1.cu
rout2.cu
power.cu
back.cu

and if i drop a via it goes from top to bottom and if i drop a via in bottom it goes from bottom to top

8

Thanks andy

I have the option to place blind and burried vias
so the answer according to you if i have to connect to ground then i just have to drop a via thats all it will automatically connect to ground plane. the only thing i need to do is draw a ground plane on the ground layer

9

As direct and short as possible.
And put the blocking capacitors (mostly all that I can see in your schematic) as close to the Vin pins they’re supposed to ‘support’ as possible.
Or in other words, don’t use long tracks to connect them to the device as that defeats their purpose.

Amount of devices looks pretty intimidating and now I’m convinced more than ever that I couldn’t have helped you there more that I already did.

PS:
Is this special routing for run-time (differential pair) of sorts? Just wondering as the net is the same.
I would have just gone to one of the pins and connected the other one sideways, not wasted so much board space.

Essentially pulled the via closer to the two pins.

PPS: You know that you can set up different via diameters and change which sort you drop depending on situation?
Just in case you need smaller/bigger ones than the 0.6 version that comes standard.

10

can you please help me on how to draw ground layer

i selected add filled zones marked in red in shows me a bunch of nets infact my schematics has analog , digital ,chassis ground if i remember last time a guy mentioned all these ground points are one and the same . so can somebody please help in drawing ground plane .

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Regards
Nick

12

To make it easy on the right hand side of that window under ‘Display’ select ‘alphabetical’ for a start.
Then YOU need to know how you want or have arranged your devices on the pcb to get the ground planes sorted.
If you got the analog devices bunched together in one corner and the digital ones in another you can make two ground planes on the same layer. How you connect those with each other is currently above my knowledge - that’s for you to find out.
As for the chassis GND, that’s usually connected at one point to PE in case you got mains going into your device… I have no idea how you connect to it when you got human safe voltages only.
Also depending on use case of your device you might need to think (& add) ESD and surge protection and get them to play nice with your ground stuff there to make sense.

PS: if you draw another fill area in an existing one and you get an error message that DRC doesn’t like it, increase the ‘Priority’ in that dialog there.

PPS: did you get that two-track-failing-to-join-problem sorted by now and/or what was the deal there?

13

Thanks Joan

The 2 track width of different sizes which was failing to join i connected them using a 0ohm resistor then it worked fine.

Regards

14

guys just a quick question if i connect a pwr_flag to any chasis ground as in the bellow image
would that create any netlist

Regards

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16

kicad is connecting to wrong netlist

hello everybody i notice one strange thing in kicad
in the bellow picture we see that Pad F5 has a net name LCD_DATA0 this is automatically generated by netlist

but if you see my schematics F5 pin is not connected to LCD_DATA0 at all

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may i know why kicad is connecting it to wrong netlist

17

Can you provide your design files?

1 Like
18

please find the attached design file

F5/G5/H5 pins of U5 are called LCD_DATA0

19

Did you check E5, G5, … as well?
What net do they have?

20

even E5 , G5 have LCD_DATA0

but in my schematics all the pins E5,F5,G5,H5,J5,K5,L5 must be connected to VDDS_DDR not to LCD_DATA0

why kicad automatically says these pins must be connected to net name as LCD_DATA0

21

check if LCD_DATA0 connects to VDDS_DDR somewhere…

KiCAD does chose the net name by chance? (not sure) … anyhow, there is no switch or option to tick that you can say this is the net name you want (yet).
If you want a definite net name use a global label and only ONE for that net.

22

no where in my schematics LCD_DATA0 is connected to VDDS_DDR
and why all unamed net name kicad has automatically named them to LCD_DATA0

23

or is it ok for kicad to name the net name as what ever it feels is comfortable and the pad/pin number is the one that matters

24

Can you post .sch and -cache.lib files too?

25

A green track going from one pin to another = minimum requirement to be a net.

If you don’t have a:

  • local label
  • global label
  • or hierarchical label

tacked onto that ‘net’ then kicad chooses one of the pins as the namesake, afaik randomly (might be tied to position in schematic, who knows), power symbol pins have highest prio.

If you got a label attached to a net kicad takes the label as net name.

If you got a power symbol (special symbol with hidden pin etc.) than this overrides above options and is the namesake.

So, the order for labels is roughly this:
power symbol pin name > global label > hierarchical label > local label > pin name1/pin name 2

If you got 2 labels of the same prio level, KiCAD chooses ‘randomly’.

As for your particular problem… KiCAD doesn’t do stuff like this wrong usually.
Somehow, somewhere in your schematic you tied these nets together.
Maybe through a power symbol, maybe via some different net on some sub-sheet/etc…
For example… if you have RandomNet attached to VDDS_DDR in some place and LCD_DATA0 attached to RandomNet in some other place and KiCAD ‘likes’ LCD_DATA0 most… all those nets will become LCD_DATA0…
Again, check your nets… you made a connection somewhere.

Unfortunately KiCAD isn’t able to highlight wires/nets in EEschema afaik.
EESchema is really due for some overhaul :slight_smile: