Two track failing to join

Received your .pdf and .lib. First look: on pg. 6, you have a global label sharing a wire with a local label (SYS_BOOT0) and power symbol (VDD_3V3A). As Joan said, Kicad will randomly choose net names (from what’s conencted) when they’re connected this way.

I noticed you use hierarchical sheets, but not hierarchical labels. Having global labels everywhere like you do now can lead to issues like what you’re having (similar to misuse of global variables in programming). I’d recommend you switch to hierarchical labels and route them on your “sheet page”, pg. 1.

Also, Ctrl+F’ing label names helps find spots where you might have misnamed a label or whatever, too. Not saying this is what happened, just a freebie.

EDIT: I also agree, I’ve never had Kicad misname/make unintended connection to a net.

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I sympathize with Nick123 on this, I have a 100 pin microcontroller on a sub sheet and there is no way to sensibly draw 70 or so pins as hierarchical pins on a hierarchical sheet symbol. Global names seems to be the only practical way to connect to other sheets when too many connections are needed

Some of the connections can be locked together in the buses. And it is easier to pull out such a bus outside of the sheet than separate signals. For example on Nick123 schematic: LCD_DATA[0…15], AIN[0…5] can be treated this way.

Take a look at video project from KiCad’s demos folder.

That works if you have nice wide buses. My last design was a re-draw to KiCad of a Cadstar design and I wanted to keep the existing net naming

i have multiple power component as i have attached here in this message like VDD_5V,VIO,VDD_MPU,VDDS_DDR and so on there is only one pin to this component and all pins have pin name as VDD when i create a netlist all power pins are connected i thought pin number is important not name but in this case looks like pin name is important as well is it only in case of power component or is it true for all components

only after i renamed the pin name from VDD to VDD_1V8 this issue was resolved
can somebody please explain am i doing something wrong or pin name for power component must be unique

It seems the pin is set to invisible.
Hidden pins are connected if they share a name.
for a detailed discussion about that see: https://bugs.launchpad.net/kicad/+bug/912529

(At least the one in the bottom screenshot.)

Edit: i missread @Nick123’s post. In short:
Power symbol pin names dictate the net name. (They are used like global labels to connect nets.)
Kicad derides that all hidden power inputs are treated like that.
In this answer and all answers below i wronglyi assumed, that he was talking about a pin of a normal symbol.

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thanks rene is it true for all components
rather i renamed the component as i mentioned previously from VDD to VDD_1V8 i hope that should be fine

let me know in case any issue then i can go and set all pin name to visible

In the bug report they talk only about power pins. Maybe pins with electrical types other than power are not connected automatically.
To be honest after reading the bug report i would not use hidden pins at all.
(I have symbols with hidden pins. I need to check my PCBs if there is a problem because of this “feature”.)

very true thanks for the help anyway

Rene

but if i set to visible the ground component has 2 same names one is pin name and other is field value both set to GND which of them is important

please let me know

Power symbols are special. They are treated somewhat like global labels. According to the Transwiki (Powersymbols) pins of powersymbols have to be set to invisible.

Short version from the linked wiki site:
pin invisible and has the name of the desired net name
electrical type is power input
Ref designator starts with #
value the same as net name
under preferences check power symbol.

I think that’s exactly the reason why your invisible power pins got connected. There is no separate pin type for “this is a logical pin” and all invisible power pins are treated as if they are part of a power symbol.

you just now said set them to visible
now why do you suggest to make them invisible again

In symbols which represent parts (Devices that have a footprint): set them to visible. (unless you want the behavior as documented in the kicad documentation. Do be honest you probably don’t want it this way.)

In power symbosl (GND, VDD, …) which are used like global labels: set them to invisible.

that is what was exactly before in the previous image VDD_1V8 it was invisible but all pin names were VDD hence all were connected which is wrong

Ok now i understand, sorry for the confusion.
(I somehow missed that explanation in you post.)

In that case:

Yes powersymbol pin names need to be unique if you don’t want them to be connected.

There you go thanks i have made them unique now

:slight_smile: