I have an LT Simulation up and it shows how the op amp goes into saturation and this is my reference.
I really would like to learn how to stay in KiCad with the simulation and get nearly the same results of simulation.
So i read my way through a lot of posts and set up / use two files below.I checked the pinning in the simulation and everything seems to be fine but I don’t get any useful results even similar to LTSpice!
Sure. Sorry. I get DC at the output and no voltage swing at all. I have a feeling i may have wired it up wrong but i cannot find it. I’ll post more details later.
I don’t know this OpAmp but for me it looks you have no DC supply for its (+) input. If it is typical OpAmp it should have at least big problems to work as it is not able to ensure the same potential at (-) input.
It is exactly what I would expect if (+) input is at one rail voltage (probably - one) and (-) input can’t reach the same potential ever.
If V3 ampl would be 18V (6+12) than it is possible that (+) input will reach a level when OpAmp will go into working range.
It is exactly what Piotr is suggesting: If you add a resistor between in+ and the middel voltage (6V), then you will have an adequate dc potential also at the in+ node, and you will get an approximate square wave output.
Hi BlackCoffee et al,
i tried the export feature and it works nicely. Its just that LTSpice is so clumpsy I will not use it.
However comparison of my Circuit in LTSpice and export from KiCadto LTSpice showed the same error.
That means that something is wrong with my modeling.
I would really like to use the LTC.lib from LTSpice but if i use it this happens:
Any thoughts on how to prevent this error?
This error is why I started tinkering with a self-made model. (Besides it is a good thing to know how to set up a Spice model.)
Since I copied the subckts from the LTC.lib I thought it should work and give the same results as in LTSpice. But it did not.
Here is the exportet circuit:
That is 100% correct but I would word it differently: Every op amp input requires some DC bias current. Your + input has no source for that. Old op amps such as the 741 might have 500 nA maximum input bias current. CMOS op amps might have only a few pA. But you need to have some DC current path to both op amp inputs.
Generally you should try to match the thevenin DC resistance connected to the two DC inputs. But matching requirements depend on the resistance and op amp bias current. So if your bias current is 100 pA maximum and the input resistances are mismatched by 10K ohms, that will cause only a 1 microvolt offset at the op amp inputs.
I didn’t wanted to search for datasheet. As OP have written that LT Simulation works with his schematic correct than I assumed that may be it is not 100% typical OpAmp and may be it is some construction I have never meet with for example integrated initial polarization (with GΩ resistors) or even it is not OpAmp but other amplifier.
So I wanted to write what I see surprising in schematic but I was not 100% sure of it (even 0.01% makes me not saying that it is such or such).
