I just want to preface this question by disclosing that I’m very new to Kicad so bear with me.
In my PCB design there are two tracks that can carry up to 12A. I used the calculator built in Kicad to determine the width of the tracks (using trace thickness of 0.35 mm) and it came out to ~9.3 mm. Obviously this is large, so I thought using a zones would be appropriate. Below is what I was thinking. Is this a good idea? Is there a better way of approaching this? Also, I find that the zones are fairly close and I’m not sure if that is enough clearance with such high current, but I don’t know to avoid that. Any suggestions are greatly appreciated.
That looks about right, although I do not know how wide your tracks are.
You can make the gap next to the IC a bit wider, but the width of the gap between the copper zones is mostly irrelevant. There is no voltage over it because it’s shorted by the shunt (or Hall sensor) in your IC (I assume it is that).
The track width you calculated probably was based on a temperature rise (default 10deg. C) If you extend the zone to area’s where there will not be current, then those area’s still work as a heatsink to lower the temperature of the zone.
Based upon what you stated about ~9.3mm, this would imply you are using 1oz copper (reversing Kicad value).
The concern is Kicad’s calculator uses IPC-2221 for this and this has been superseded by IPC-2152. Using an IPC-2152 based calculator results in a trackwith of 24.4mm (for 10C temp rise, 1oz copper)
Now some say IPC-2221 is “good enough”, IMHO it isn’t… and a doubling of the needed trackwidth is testament to this. Ill leave it up to you with regards to what width you feel is correct.
As to the layout… I agree with @paulvdh, the separation between the two shapes can be very small, the minimum etch width for this weight of copper (8thou?) because the voltage difference is going to be in uV as the associated SOIC8 part will have a resistance around 100uR
What I would do however was move the terminals as close to the part as possible as this will minimise the volume of copper conducting the current. Likewise I would utilse both sides of the PCB to spread the current across two layer - The banana plugs will provide a double-sided connection so you just need some supporting via’s around the sensor
The usual rule of thumb is a “standard 0.3mm” via with typical plating is good for ~0.5A (for a 10C temprise)… likewise x-number of such a via ~ one via of x-time the diameter … So there is a happy medium of a number of vias of a specific diameter
Thank you very much. That all makes sense. Do you mind providing me a link with the IPC-2152 calculator that you used? I looked up one online (https://twcalculator.app.protoexpress.com/) and it is saying that the necessary trace width is ~20.9mm for 1 oz copper. I just want to make sure I get this correct.
I also see that using 2 oz copper would be highly beneficial in this case as it reduces the necessary with to ~11.5 mm. Will having the layer on top and bottom also reduce the trace width or does that just limit power dissipation?
I use SaturnPCB A really handy toolsuite.
One thing to consider about IPC-2152 is they provide curves so all calculators that exist are producing a “best fit” based upon these curves to produce convenient calculators
This is something to consider when you use these as it doesn’t mean one is correct and another is incorrect, there is just a varying degree of inaccuracy in their model - Yes I know this doesn’t help
Using two outer layers will half the current each will carry (assuming they are identical, with identical impedance ) and thus you can reduce the track width from ~20mm down to ~6mm.
The moment you start using internal layers to help share it starts getting complicated as FR4 is a very good thermal insulator and also such internal layers will be heated by other parallel layers.
IPC or not, all calculations are theoretical. When you plug in the thick cords they will act as heavy duty coolers. On the other hand if you leave the device in the back shelf of a car in the summer sun it will exceed the limits without any current.
I tend to be conservative, my experience is with PBC’s not Kicad. I worked in Aerospace and Automotive.
1st: The dominant failure mode of excessive current on a PCB trace is overheating a portion of the conductor causing it to start to lift off the board material. Once this happens the temperature of that portion of the copper gets even hotter resulting in a domino failure effect.
2nd: The feedthroughs have no where near the current capability of the surface copper. And are worse the smaller the via hole.
3rd: The copper layer is specified as oz/ft^2. This is because there is no guarantee of the thickness in any given area. I will concede the newest processes are better at controlling plating informativity. But keep in mind you are purchasing “hobby” quality boards not mil spec or automotive spec boards.
4th: IMHO the IPC is a guideline which I view as a minimum. Just as I wouldn’t but 50V on a 50V capacitor, I wouldn’t put the IPC “calculated” guideline on a PCB without some significant derating.
My experience is from working with PCB’s where we had the opportunity to test prototypes and learn how important the derating is.
So unless you have a critical size issue (with the size of the PCB that is) I suggest you err on the side of reliability.
of course top and bottom (roughly) halve it again. The basics is that resistance,and therefore heat rise, is proportional to total copper cross-section area.
Your original question was about a method - traces vs. fills. but if you are asking “how to carry lots of current and how critical is it?” - that’s a different issue which i assumed you understood.
To really reply we’d need to know more about the actual load. Constant or vary-ing; duty cycle (peak:average ratio), and any other factor that might influence heat. More copper is better; but note also constriction points - like a chain, its only as good as its weakest link - which becomes a fuse, in a way you don’t want.
1 Oz copper is a “standard” and fine for most low power circuitry. That said, when i have needed o carry LOTS of current, i typically specify 2 Oz. But its also a cost trade off. If you have space for 1" wide traces, and 2 Oz copper quadruples the price (not uncommon) do the wide traces. using top and bottom is great too, so long as you can effectively direct solder to both sides. Vias wont cut it.
And dont neglect the ground return. It needs to carry the same current.
well, if we are being that picky, equally wrong:-) the resistance will in fact fall by half if the cross section is doubled, and therefore generate 1/2 the heat. dissipation is another issue. Statement correct as written, but yes, heat dissipation is better the larger the unshielded surface area.
Its not semantics, its real and you gave the OP advice that is not accurate (or even close)
The bottom clad (of equal size) will absolutely NOT carry 1/2 the current. The current in the bottom clad will have to go through the small vias shown near the gap between the two sections. Vias have terrible conductivity compared to copper clad.
When dissipating heat with clad on only one side of the board. A fair amount of thermal energy passes through the board and is dissipated on the opposite FR4 surface. When you add clad to the back of the board you essentially remove that dissipative area and replace it with a different dissipation (higher) capability. So it is NOT purely additive as you state.
This really does not warrant a reply, but your assertions are just so far off that i felt compelled, once and only once. As usual, reasonable people will be driven away due to these silly, anal-retentive arguments.
Far above i stated that via are not sufficient. Strike one. But in any event he clearly shows large, through hole tabs that will directly solder to both the top and bottom. Strike two. I checked his drawing and noted it in case i misinterpreted. From what i see, you never read what i wrote nor looked at his diagram. So please stow the flames.
I am trying to keep it simple. Worry about the important, and only then the less important.
Actually it isnt far off… the IPC calculators are base upon extracting “best guess” data point from the PICTURES of the curves in the spec and then doing s best fit against these extracted curves. As a result there will always be an error but typically all the calcs are around 1% from the pictures over the same very small range of current. Also they clearly state single layer (internal or external) with the only modifier they consider valid being whether there is a plane nearby which can act as a heatsink
The moment you talk about using both sides you are drifting further and further away from the empirical test set and you either work with experience or another set of tools: hyperlynx or ansys
As someone that regularly makes PCBs that carry 100+ amps do you thing these “calculators” are used?