Hi
I have a doubt. I am designing two layer board. Both layer i am using as a signal layer and going to create a zone as a ground net. PCB carrying maximum of 5 Amps current, temperature rise of 10 deg Celsius. can any one suggest the trace width of data signals and power signals.
Because in my previous PCB board, the same specification as mentioned above but i have selected the trace width as 0.25mm for data signals and 0.4mm for power signal. Its working fine but some leakage current occurs in the board.
Data signals aren’t relevant here. The only relavant thing is the width of the power line and even that only there where the high current flows. Most probably only some parts of the power net carry high current. You should identify it, measure the length and then you can use the calculator which comes with KiCad.
5A is quite much, according to the calculator it would need 2,76552mm for 10deg/20mm length. You should use zones instead of traces.
Be aware that adding a GND zone is not a magical thing that automatically connects everything with low impedance. Especially in two layer boards. With these restrictions you will have other traces that split your zone. You either need to ensure that you do not have any traces on the layer where the zone is or you need to have the zone on both layers and create stitching vias where necessary.
Make sure that the high current path or any high frequency paths really have a low impedance connection between the source of power and the user of power.
For high power applications it might make sense to really think about connector placements. Might be a good idea to have the supply connector and the connector for the high power stuff right next to each other. (Assuming you only switch the high power stuff but have the real user external.)
If I punch in your numbers in the calculator for 7pcb, it suggests for 5A and 10C above ambient a width of 7.19mm for internal layers and 2.77mm for extnal layers.
But be carefull. I assumed a copper thickness of 35um, which is the most usual copper thickness, but thicknesses may vary.
Sometimes the copper thickness for internal layers is thinner.
35um being the standard 1oz copper. There is usually an option for 2oz or 70um, with consequences on cost and feature limits.
Sometimes inner layers in multilayers are 0.5oz - check with your vendor.
When running at high currents, also consider current rating of the vias.
I just started KiCad’s PCB calculator and I saw no mention of Via’s.
You can get a rough estimate of the conductivity by using the circumference of the via hole (not the guard ring ofcourse) and use that as “track widht”.
The copper in the via’s is always thinner as the copper layers, Via’s are made by first making a very thin slightly conductive layer, and then it gets thickened by electrolysis, and the same electrolysis process also thickens the copper on exposed layers.
Vias are a area where being conservative is warranted (IMHO).
When I was in Aerospace, we would section a sample of vias on every board lot. Although things have changed in board the copper of the via ID is not as “ideal” as that on the surface due to the rougher surface of the Via ID. Also the thickness is not uniform, becoming thinner near the center of the board. Board mfg technology has likely gotten better but the physics still applies.
For my boards the current carrying via’s have a 0.8mm hole and I like to double them up where possible. I’ve not yet needed a via with a 1 mm hole but I would not hesitate to increase the hole ID if needed.
I agree, it is common to see via breaking out of their pads or not fully plated around.
These only receive a basic continuity test by default, unless stricter QA has been agreed and paid for.
