Too many parameters for subcircuit type

Hi, I am a newbie. I successfully used eeschema to create a hit and hold solenoid driver
circuit with basic components (cap, res, v source, inductor). I am now trying to model a
more sophisticated circuit which includes a diode, bjt and pMOS switch. For the diode and
transistor, I am using models downloaded from the manufacturer and they don’t report
errors (diode 1N4148, and transistor 2N3904). For the pMOS I downloaded the model
from Fairchild (FQU17P06), but when I run sim I get an error:

Too many parameters for subcircuit type “fqu17p06” (instance: xxm1)

What am I doing wrong?



.SUBCKT FQU17P06 20 10 30

Rg 10 1 1

M1 2 1 3 3 DMOS L=1u W=1u

.MODEL DMOS PMOS (VTO={-3.5*{-0.00034TEMP+1.0085}} KP={9.3{-0.000014*TEMP+1.00035}}

  • THETA=0.056 VMAX=1.95E5 LEVEL=3)

Cgs 1 3 610P

Rd 20 4 42m TC=0.0042

Dds 4 3 DDS

.MODEL DDS D(BV={60*{0.0008*TEMP+0.98}} M=0.5 CJO=235p VJ=0.8)

Dbody 20 3 DBODY

.MODEL DBODY D(IS=9.5E-13 N=1.0 RS=23.3m EG=1.17 TT=92n)

Ra 4 2 31.3m TC=0.0042

Rs 3 5 3.2m

Ls 5 30 1.0n

M2 1 8 6 6 INTER

E2 8 6 4 1 2


Cgdmax 7 4 950p

Rcgd 7 4 10meg

Dgd 4 6 DGD

Rdgd 4 6 10meg

.MODEL DGD D(M=0.50 CJO=950p VJ=0.52)

M3 7 9 1 1 INTER

E3 9 1 4 1 -2





That’s not enough information to be able to figure out the problem. At the minimum, can you post a screenshot of your schematic and also paste us the SPICE netlist? (in the Simulator menu: Simulation -> Show SPICE Netlist...). Even better if you can upload your KiCad project somewhere so we can download exactly what you are using.

Hi, Ste - Thanks so much for the reply. Here is a GoogleDrive link with my project.

I uploaded the .pro, .sch and the .lib for the pMOS. If I missed something let me know
and I will add it to the folder.

If I remove the pMOS the simulation seems to work as I would expect. Voltage on my
solenoid goes from 0 to about 6V, and the current goes from 0 to about 27 mA.

The idea of this circuit is to “hit” the solenoid with 12V for about 25ms or so to open it, and then drop the
voltage to about 6V to “hold” the solenoid open. It seems as though I got pretty far along in just a day,
but then I got stuck on the pMOS.

Thanks for any assistance!
Gregg G.

Cool. Thanks for uploading the files somewhere. I believe I located online the exact same BJT and diode model you are using, so I should now have the complete picture what you’re trying to simulate.

So you actually have a few problems here. Two are your fault, but one is not.

First is the BJT. You used KiCad symbols from the pspice library for every component except for the BJT. The problem this creates is that the pin order for the TO-92 packaged 2N3904 doesn’t match SPICE convention, which is: 1=collector, 2=base, 3=emitter. One way to fix this is to simply use the pspice symbol for the BJT…but I have a feeling I know why you didn’t. It’s because that symbol has the 4th connection to the “substrate” which is confusing. Therefore, I think the best way to fix this is to keep using the same BJT symbol you had, but use the Alternate node sequence setting to remap the order of the pins as shown below:

Next, is the PMOS symbol. This time you used the pspice symbol, but because you .LIB file specifies a subcircuit you need to feed it the exact amount of pins it needs. If you look at the .LIB file, the .subckt line specifies three pins in a specific order: 20, 10, 30.

.SUBCKT  FQU17P06   20  10  30

Because your symbol has 4 pins there’s a mismatch here, even if you leave that 4th pin (the MOSFET body/bulk in this instance) disconnected. Also, good .LIB files will tell you what pin is which, but this one doesn’t. Luckily, the ordering follows typical SPICE convention (1=drain, 2=gate, 3=source), so you don’t have to reorder the pins like with the BJT for this specific subcircuit. BUT, now there are two ways to fix this. You can still use the Alternate node sequence to fix this by simply telling it to use pins 1 2 3 which effectively trims off the 4th pin, like shown below:

Alternatively, you can pick a new symbol which only has three pins and reorder it as needed (just like with the BJT above). I prefer this method because 3-terminal power MOSFET symbols show you where the body diode is and how it’s oriented so it’s easier to design with.

The last problem is with the FQU17P06.lib file itself. ngspice (or maybe just Eeschema’s parsing of SPICE files) seems to reject nested brace symbols { } in evaluation expressions. Therefore, to get this running I needed to replace any nested brace symbols with parentheses. I will throw it to @holger if he knows if this is a known issue or not…or if there’s a better workaround that I don’t know about. Regardless, I attached my version of your entire project below so you can witness all these changes yourself. (3.8 KB)

Hey, Ste - Sorry for the newbie mistakes. Ha, ha - as far as the non-pspice BJT symbol, I didn’t even notice that the QNPN symbol was in the pspice library! Now that I look at it, the 4th connection would have been a little confusing. It looks as though the way to have handled it might have been to leave the S terminal floating and maybe use the “noconn”, yes?

As for the pMOS, I used the symbol from pspice and then added the .lib because I couldn’t find another symbol in the “choose symbol” menu! I didn’t know to look at the “pin order” or “pin count” or how they
got specified. Just my basic ignorance of the software. Thanks for detailing how that works! You
mention using a different symbol with 3 pin connections - where could I find those?

As far as the { vs [ , whew, I don’t know that I would have ever figured that out!

I’ll get these changes incorporated today and review your details more thoroughly. I sure appreciate
the help for such basic errors. I can tell you in general I was really impressed with how easy it
was to get started with the whole package, especially for a newbie to EDA!

Thanks again for all your very detailed help and for the zip file!
Gregg G.

Hi, Ste - Just some more information for you to consider. I spent a bit of time studying everything that you said, and running the model. I have a few observations that seem to indicate something is still not quite right.

I posted a question on with regard to a simple “hit and hold” solenoid driver.
Several people were very helpful - with both a simple solution, and the more complex solution which
is this design with a transistor and pmos. The idea is that C1-pad2 sees 14V at startup and then starts to decay quickly. Q1 should see enough current at startup to switch on and create a ground path for
the M1 gate. Therefore, M1 should switch on at startup and thus bypass R6. So I would expect to see just about 14V at L1 at startup and until M1 switches off. The RC timing is supposed to be such that
Q1 turns off at about 25 ms. When Q1 switches off, M1 should quickly shut off and thus remove the
“bypass” for R6. With R6 being 300 ohms, the voltage at L1 should drop from 14V to about 6V.

  1. My .tran statement is (.tran 1ms 250ms uic). I’m not sure if the “uic” part is what I really want.
    Evidently LTSpice has a “startup” option. I don’t think I am specifying the initial conditions anywhere,
    so that may be a problem.
  2. The response at L1 is not what I would expect. It slowly rises to about 12.9V at 25ms, and then decays to about 10V. I would expect it to almost instantly rise to 14V, hold until 25ms, and then decay to about 6V.
  3. If I completely remove the pmos, the voltage at L1 goes from 0V to about 6V in less than 20ms. The 6V value is what I would expect if my V1 is all running through R6. So this seems to tell me that the pmos is not working like I would expect.
  4. It seems as if M1 is only “partially” switching on, and then doesn’t completely switch off.
    If M1 isn’t “completely switched on” at startup, that would explain why the voltage at L1 doesn’t
    “jump up” to 14V right away. Likewise, if M1 doesn’t “completely switch off” at 25ms, that would
    explain why the voltage at L1 doesn’t drop to 6V.

I will try to get the LTspice model/input for comparison sake. Obviously I am a newbie, so I was trying to
reproduce the results of a known model so I could then explore and make modifications from there.

Sorry for being so long winded, and perhaps showing more ignorance of basic electronics design/function!

This is the result I was trying to reproduce.

Yes, Eeschema/ngspice will auto-connect the substrate to ground. This will work on your BJT because the .LIB file contains a .model. It doesn’t work on the PMOS because the .LIB file there contains a .subckt.

All I did was type “pmos” into the symbol library filter search bar:

It seems to work fine for me. I added labels (to make the plots easier to read) to my version of your simulation and it seems to match up with those LTspice plots. Only thing that’s significantly different is the delay in start time. I can show you how to do that if you really need it. It involves changing your DC voltage source to a PWL (piece-wise-linear) voltage source. Your DC source works at the moment only because you have uic specified. It forces all voltages at time=0 to be zero volts. If you didn’t have that there, it would not work because it would be 14V at time=0.

Ah, I see you get the same results as the LTSpice model. I will have to go over my install with a fine tooth comb. Maybe I don’t have something installed correctly. I get different results with the zip file you sent back.

I do see now how to find the other symbols by using the search tab.

I am running Debian Buster and installed from the Debian package repository.

I’ll let you know if I find an installation error. Thanks for all your assistance!

A couple things:

  1. What happens if you change the 1uF to 1u for C1? You normally aren’t supposed to use F since that means “femto”, so you’re technically specifying micro-femto, i.e. 10e-6 * 10e-15 = 10e-21

  2. Have you set up the ngbehavior property as described in this tutorial?

I changed C1 value to 1u (instead of 1uF), but no different result.

I do have a file in my home directory called .spiceinit with the “set ngbehavior=ps”. I think I have this in the right place, because if I delete the .spiceinit file eeschema aborts when I try to run the sim!

My eeschema version is 5.0.2+dfsg1-1
ngspice compiled from ngspice revision 33

Yeah, man. Not sure. I would suggest installing the latest version of KiCad just in case. I think several simulation-related bugs were fixed between 5.0.2 and 5.1.7. Beyond that, I don’t think I can help any further.

Please check what ngspice version you are really using.

Put something like


as a text box into an empty Eeschema window, run the simulator and watch the output.

1 Like

Hi, holger -

 I followed your instructions - uh,oh.  The output is:

Circuit: KiCad schematic

** ngspice-30 : Circuit level simulation program
** The U. C. Berkeley CAD Group
** Copyright 1985-1994, Regents of the University of California.
** Please get your ngspice manual from
** Please file your bug-reports at
** Creation Date: Tue Jan 1 13:07:33 UTC 2019

I installed the buster backport for ngspice, and when I run “ngspice -v” it reports compiled
from “revision 33”. But it looks like I’m actually using version 30? I’m guessing that’s a
problem, yes?

It is probably not a problem. ngspice-30 should handle your circuit as well as ngspice-33.

But there is a misunderstanding: KiCad/Eeschema is not using the plain ngspice executable that you have already installed. It is using the ngspice shared library instead. So in addition to your install you have to install libngspice0 (see One needs to install both to get access to some advanced ngspice features.

1 Like

And to your circuit:

If you are interested in simulating a circuit start-up, you should not let the simulator choose any starting conditions (uic or not or whatever), but you should take care of these conditions yourself (as Ste has already suggested).

If you look at the original plot, you will see that the 12 V power supply is switched on only after 10 ms. Between 0 and 10 ms everything is at 0.

The combination of V1 and Timer may be emulated by a PWL or PULSE voltage source.

The ngspice manual, chapt. 4.1.1 about the PULSE source:


Name Parameter
V1 Initial value
V2 Pulsed value
TD Delay time
TR Rise time
TF Fall time
PW Pulse width
PER Period

So you may us a V1 with parameters

PULSE (0 12 10m 1u 1u 1000m)

Start with 0, after a delay of 10ms rise to 12 V within 1u, stay there until simulation finishes (pulse witdth PW is longer than simulation time, fall time therefore does not matter). Critical is the rise time TR (here assumed to be 1 us), because it influences V(pulse). You have to decide how fast you will switch on.

1 Like

Hi, Holger - Thanks for the info regarding the shared libraries. I was able to install them and add the PULSE source. Getting close, but I still have a problem. Q1 seems to switch on at startup and pulls M1 gate to ground. The problem is that M1 doesn’t seem to “switch on completely”. L1 voltage slowly increases, but doesn’t “jump up” to 14V as I would expect. (I have a 14V wall wart, so that’s the discrepancy between 12V and 14V).

I tried to use the simulation “probe” to look at the voltage on M1 drain and source, but I couldn’t get the “probe” to work. I’ll look at the documentation some more to try and figure out what I’m doing wrong.

Ah, so I think I’m a dope. I think my problem is correctly plotting the voltage at the coil. I guess I was plotting L1-Pad1 (which is the end of the coil). If I wanted to plot the voltage at the front of the coil (L1-Pad2) I could plot D1-Pad2. When I do that it looks more like what I would expect, except for the couple of spikes between 35-40ms. Maybe my time step is too big? I’ll run again with smaller step.

So this is very interesting. I reran with (.tran 0.5ms 250ms uic) and get a completely different result!

So I experimented with different step sizes and got some weird results. Finally ran with
(.tran 0.05ms 250ms uic) and started to get what I thought it should look like.

Obviously, 250ms is way too long a sim time, so I cut it to 100ms and found that
(.tran 0.25ms 100ms uic) was about the “largest” step size I could use and get good results.
I’m wondering if I found a “bug”, if my “installation” is quirky, if I was simply overlooking “convergence” criteria, or something else overlooked on my part. In this last plot you can see just a small “blip” in
the coil voltage right before 35ms. Maybe 0.25ms is the “edge” of the convergence criteria, yes?

Anyway, let me know if any of this makes sense, and if you think all my problems were simply
“operator error”! This has been quite a fun learning experience. Sorry to take up your time
on newbie errors.

I would check out section 15.3.9 of the ngspice manual:

Make sure you understand the difference between tstep and tmax. tstep is the print interval and tmax puts an upper-limit on the internal time-step computation interval. Sounds like your errors above are due to not specifying a tmax. Without one, the SPICE engine can auto-calculate time-steps which step too far or around features you are trying to look at.