They give min and max (not a typical), but the average is:
(1.143 + 1.397) / 2 = 1.27mm.
which is same as saying 1.27mm +/- 0.127mm.
The firs one from Infineon that Arcatus links to definitely has a nominal pitch of 1.14mm:
And over the four pitch distances that becomes a difference of:
4*(1.27-1.14) = 0.5200
… Or: each side is 0.26mm off. For a handful of home built boards you it’s not such a biggie, worst case you bend the pins a bit, but it’s not nice for bigger series for PnP machine placement. Normally you’d build a few prototypes before going into production, but it’s easy to fall into things like this if you have to find alternative parts because of chippageddon for example.
OK, that is odd. I would make fatter pads that handle both and call it a day.
Anyone attempt to find the JEDEC standard for TO-252? I usually think of a 2-pin (not a 5 pin). But I like to make fat pads anyway. If I were presented with that contradictory information before designing the board, I would make the pads wide enough to fit either one. Clearly there are limitations to that if spacing is tight.
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In the Fairchild Datasheet I posted earlier the 1.14mm pitch TO-252-5 is specified as conforming to JEDEC TO-252AD
That means 1.14mm pin pitch is the standard.
Doesn’t change the fact that some manufacturers do not respect that and make TO-252-5 with 1.27mm pin pitch.
It’s a total mess.
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These questions, in part, explain the existence of this: https://forum.kicad.info/t/kicad-the-case-for-database-driven-design/34621
For many years now I have observed that component data sheets are often in error when it comes to physical dimensions. There are probably several reasons why this happens. The part is designed in one system of measure and the conversion is done by another, less skilled person so it is not exact. Sometimes there are rounding errors. An exact conversion or even an exact number in the same units used for the design process has too many decimal places so some are just omitted. Then there is the tolerance range. It seems like in this case a number representing the low end of the tolerance range was used.
Two things to keep in mind: first, electrical engineers are not mechanical engineers. Yes, they should understand these things, but … And second, the task of publishing the specifications may not be done by the design engineer. It may be handed off to a less skilled employee. A MUCH LESS SKILLED one. They cost less for their time.
It is a real world. If a physical dimension does not seem to be an even number in either the English or the metric system, perhaps it should be double checked. That’s my rule and it has saved me on many occasions. In today’s world, most parts can be in your hands in a day or two. I don’t like ordering PCBs before I can make a full size paper print and assemble the actual parts on it.
I also don’t like using parts from unknown web suppliers just because they are cheap. I look for suppliers who were in business BEFORE there even was a web.
I believe that most chip makers actually buy in lead frames from third parties, so it is a bit odd to have two varieties to TO-252-5 unless the JEDEC standard allows both as suffix variations
specially to Kicad. If you decide to use a N-Channel Mosfet you have to decide between identical looking symbols what are:
Q_NMOS_DGS
Q_NMOS_DSG
Q_NMOS_GDS
Q_NMOS_GSD
Q_NMOS_SGD
further more for the 4 pin models with connected tab. Hopefully every designer knows by heart the TO220 of his IRF540 counts GDS. Otherwhile there is a wrong layout without any further warning on forward annotation or footprint assignments. Urgent time to improve this using the database and shrink the symbol library to a fraction.
You missed:
Q_NMOS_SDG
Drain is normally substrate and sits on the tab, except for some RF devices, making GDS by far the most common variant
Designs use only custom footprints; that may be created from a KiCad library footprint. Each footprint has the basic size/shape of the physical part created on the F.Fab layer (shown in blue in the image.)
The KiCad, or other trusted, 3D model is then checked against the custom footprint.
In the image, both C1 and U1 line up as expected; both on the board layout and 3d viewer.
Or how about a Q_Dual_NMOS_PMOS_S1G1S2G2D2D2D1D1 ?
FETs are really a pain, because there is no standard at all regarding package or pin assignments. But having a proper symbol (rather than a plain box) really helps the legibility of the schematic a lot.
So if you want a nice schematic, you find yourself continuously adapting symbols and footprints each time you use a new FET.
I can’t quite imagine what it might be, but it would be amazing to have a solution to this… perhaps something based on the pin-names used in symbol and footprint, like an auto-mapping for pins named “D, G and S”? Then we could reduce it to one symbol for FETs, with the differences in the footprints, where they belong…
There is a solution to this, and it has already been mentioned at least 3 times in this thread, and that is setting up a database with parts that are interesting for you.
What would this achieve?
Having a handful of generic schematic symbols is not a problem in any way. It’s not difficult to select, does not take up much disk space (compared to 3D models), and a handful of symbols is also not going to confuse users. Why would moving the “perceived problem” from a handful of schematic symbols to some extra layer of indirection by adding pin mapping be an advantage?
In KiCad, “pin numbers” are actually 4 character alpha numeric strings (meant to enable “chessboard mapping” for BGA’s and other high pin count parts. But using “G”, “D”, and “S” for pin names would just move the problem to the footprints. Now you need footprints with those pin “numbers”, and you duplicate that for BJT’s, diodes and other parts.
That’s not an interesting solution for non-companies.
While I understand and have no issue with the database use-case for some company, where multi-user use cases are important, and there may even be persons repsonsible for keeping this database up-to-date, I don’t think its a good fit for me (or most other individual users).
As a non-professional and solo user, I’m not interested in configuring and filling a database in order to use my EDA tool. I’m perfectly happy using KiCad’s built-in symbol and footprint managers, and the better these are out of the box, the less work I have to do myself.
That’s not the problem…
I disagree. It’s very confusing. Take a symbol like Q_NMOS_GDS and any given FET footprint, and you won’t be able to say if the pins match the footprint. You’ll have to check each time. As you work with a schematic, changing components due to design changes or parts availability, you have to recheck each time. Often you have to adjust footprints or create variants as the footprint’s PIN numbers don’t match the symbol’s. This process is annoying and error prone.
Agreed.
From my point of view, this would be a significant improvement. Obviously it can’t work for all parts, or BGAs in general, or abstract use-cases like this, but that’s not the case here.
For FETs, and a wide array of other parts, you can assign standardised names to the pins - D,G,S for FETs, B,C,E for BJTs, + and - for Diodes and polarised capacitors, IN+, IN-, OUT for OpAmps and probably quite a few more.
The advantage is clear - one schematic symbol works with a variety of different footprints, regardless of different vendor’s pin numbering conventions.
On the other hand, I don’t see any big advantages of the current system (other than being the status quo, of course), since I don’t think anyone actually benefits from assuming by convention, for example, that pin 1 of a LED is the cathode, only to find out later it isn’t.
And even if they catch the error beforehand, they don’t really benefit from having to edit the footprint or symbol to make things fit the numbering convention.
Thanks for pointing that out, I should have known from the BGA parts… so actually this means KiCad could already do what I envision? And I all I have to do is create some symbols that work in this way? That would be great 
Drawing symbols is a lot easier than drawing footprints and minor errors are less relevant. I understand your reasoning and there would be advantages doing it your way, but I like only having to draw/edit e.g. a SOT-23 footprint once and not having to create tons of variants with different pin assignments.
FWIW, @runger, I am in complete agreement with you.
I think that FETs on the schematic should have their pins labeled GSD, and then I can pick the correct footprint for the particular device I am using. Having the pins labeled 123 just means there is another level of indirection that needs to be navigated.
Of course, that’s the way my old system worked, so maybe I’m just biased.
That leads to a variety of TO-220 etc footprints with all permutations.
There’s no getting away from something having a big variety.
Either it’s a zillion parts and all their packages, or footprints with every possible pin permutation.
I think the latter is more manageable.
Now apply the same logic to the 14 and 16 pin DIL packages for 74LSxx and CD4xxx series.
You end up with the Eagle linked footprint and symbol world