This regulator uses TO-252-5 and lists pin pitch as somewhere between 1.143mm and 1.397mm (safe to assume that it’s typically 1.27mm)
The first link for infineon’s version of the package lists 1.143 on the drawing, but “Min. Terminal Pitch” as 1.14 in the table above. It’s very hard to tell what the intended pitch is for these. Maybe someone at infineon made a mistake and pasted minimum instead of typical values into the drawing? In that case the footprint is just incorrect.
Besides, outer pins should only be about 0.25mm out of position while pad to pad distance is 0.34mm i.e. the package should still (barely) fit the footprint. Is it really impossible to solder the part to the board? Can you give us some pictures?
It fits, kindof, but the discrepancy was large enough for me to dig deeper, so I found these differences. But okay; lets go down that rabbithole: Lets assume that the kicad footprint is incorrect, because (?) the Infineon drawing is incorrect. Whats next?
(And: How is that even possible- TO252-5 are used everywhere, so that why I didn’t bother to do a fit-check. I just assumed that this basic standard footprint has to be correct)
Can the kicad footprint library be trusted?
I just measured three random TO-252-5 regulators that I had in my parts drawer and all of them had pin pitches somewhere around 1.3-1.2mm. None of them were from Infineon though.
It’s just a big mess in electronics packaging and such differences are unfortunately quite common, and it happens with a bunch of different packages. Some connectors are available in a pitch of 5.00mm and in 5.08mm. some SOIC’s have a pitch of 0.6mm and others a pitch of 0.65mm and those differences are too small to see, but big enough to cause problems during assembly. No in the end it’s not safe to assume anything and you have to verify whether your parts work with the footprints you have.
And there are also other gotcha’s, For example for SOT-23 it’s not even guaranteed that pin number 1 is always in the same place (but I guess the parts that deviate from the “most common” variant is becoming ever less common).
On Aliexpress you can buy USB connector assortments especially made for repairing phones. Some of them have over 100 different micro USB connectors. They all fit the same male plug, but the way in which they fit on the PCB is different each time.
Overall in industry this is a huge waste of time and energy. Because of those silly differences all bigger companies are forced to maintain their own databases with parts (and also delivery info and other stuff).
Mostly yes. But not with 100%. Every large-enough library (from any CAD-system) has the possibility for erros - and you know murphy.
And: How is that even possible- TO252-5 are used everywhere …
I know it’s unsatisfactory, but that’s simply real life. The semiconductor-vendors sometimes modify footprints or take it only as “suggestion”.
FWIW I looked into my datasheet-collection and all my used TO252-DPAK devices are with the 1.14mm-pitch. So the infineon-datasheet is not false, it differs from your other examples. Even Diodes.Inc. has TO252-footprints with 1.14mm pitch - as opposed to the 1.27mm from your example above.
The firs one from Infineon that Arcatus links to definitely has a nominal pitch of 1.14mm:
And over the four pitch distances that becomes a difference of:
4*(1.27-1.14) = 0.5200
… Or: each side is 0.26mm off. For a handful of home built boards you it’s not such a biggie, worst case you bend the pins a bit, but it’s not nice for bigger series for PnP machine placement. Normally you’d build a few prototypes before going into production, but it’s easy to fall into things like this if you have to find alternative parts because of chippageddon for example.
Anyone attempt to find the JEDEC standard for TO-252? I usually think of a 2-pin (not a 5 pin). But I like to make fat pads anyway. If I were presented with that contradictory information before designing the board, I would make the pads wide enough to fit either one. Clearly there are limitations to that if spacing is tight.
For many years now I have observed that component data sheets are often in error when it comes to physical dimensions. There are probably several reasons why this happens. The part is designed in one system of measure and the conversion is done by another, less skilled person so it is not exact. Sometimes there are rounding errors. An exact conversion or even an exact number in the same units used for the design process has too many decimal places so some are just omitted. Then there is the tolerance range. It seems like in this case a number representing the low end of the tolerance range was used.
Two things to keep in mind: first, electrical engineers are not mechanical engineers. Yes, they should understand these things, but … And second, the task of publishing the specifications may not be done by the design engineer. It may be handed off to a less skilled employee. A MUCH LESS SKILLED one. They cost less for their time.
It is a real world. If a physical dimension does not seem to be an even number in either the English or the metric system, perhaps it should be double checked. That’s my rule and it has saved me on many occasions. In today’s world, most parts can be in your hands in a day or two. I don’t like ordering PCBs before I can make a full size paper print and assemble the actual parts on it.
I also don’t like using parts from unknown web suppliers just because they are cheap. I look for suppliers who were in business BEFORE there even was a web.
I believe that most chip makers actually buy in lead frames from third parties, so it is a bit odd to have two varieties to TO-252-5 unless the JEDEC standard allows both as suffix variations
specially to Kicad. If you decide to use a N-Channel Mosfet you have to decide between identical looking symbols what are:
Q_NMOS_DGS
Q_NMOS_DSG
Q_NMOS_GDS
Q_NMOS_GSD
Q_NMOS_SGD
further more for the 4 pin models with connected tab. Hopefully every designer knows by heart the TO220 of his IRF540 counts GDS. Otherwhile there is a wrong layout without any further warning on forward annotation or footprint assignments. Urgent time to improve this using the database and shrink the symbol library to a fraction.
Designs use only custom footprints; that may be created from a KiCad library footprint. Each footprint has the basic size/shape of the physical part created on the F.Fab layer (shown in blue in the image.)
The KiCad, or other trusted, 3D model is then checked against the custom footprint.
In the image, both C1 and U1 line up as expected; both on the board layout and 3d viewer.
