I am searching tips how to handle the situation where there is big GND zone area on copper layer, buried VIAs are not allowed and other signals are mostly routed on front plane and one signal line is blocking access from another signal line to PIN.
In attached picture I created two different ways to resolve the problem. First method has one bigger GND cut-off area with two VIA’s that allows having a signal wire on GND plane.
Second approach has two smaller VIA size GND zone cut-off areas and the signal is then drawn on another copper layer instead of using the GND copper layer.
You don’t need to create keep-out areas do to this at all; if you place vias, or vias and traces, on the same layer as the zone, then refill the zone, it will avoid those new elements on the board based on the clearance settings.
One other thing to note: you have small ‘islands’ of the GND zone, connected to the main zone by very thin traces between the pads. This may be bad for your design, as others here have commented (you’ve created small antennae). The most obvious one is the area which has trace between pads 79 and 80.
I prefer to use the third solution - one 0R resistor.
Such problems depend on signal frequency. Generally the smaller the GND openings the better. But if signals are slow then any solution is good.
And as it was said openings for vias and tracks in GND would be done automatic.
Thank’s I didn’t notice that I can change the NET for VIA’s even if there is GND zone under and it’s by default assigned to it. Would 5 mill clearance that I have set as a default for everything be ok also in this VIA case?
About the antenna thing. Do you mean that the NET-R2-(PAD1) trace from PIN-79 to VIA would work as an antenna? Or do you mean the small trace from PIN 77 to GND?
The 0R resistor was is handy trick that I did not have in my mind. Just needs to document it’s purpose carefully in schemas so that it will not get removed by accident if starting to optimize things for smaller space.
This is what I was referring to as an ‘antenna’ - a tiny trace between pads 79 and 80 which connects to a small section of the GND zone which is enclosed by other traces. I’m no expert but I’ve read plenty of advice here to avoid such things, especially when this small section of GND zone won’t provide any benefits. You can stop this from happening by placing a small keep-out zone in the layer of the GND plane on the left side of pads 79 and 80 so that the GND zone won’t leak into that space.
Did I understood the reasoning correctly: Because I have the cut-off area to GND zone on the right side of NET-(R1-Pad1) while connecting to VIA, then I should do the same thing also on the left side of same trace so that the potential difference in the both sides of the wire would be close to each other and thus reduce the radiation?
I do but as Rene pointed out, somehow the "show zones in outline mode: got activated!
BTW: yes, I have several methods of “backing up:”…most important one being “archive” projetc & then move it to a thumb drive…,.
Thanks much for giving your time on this matter.
What appears to be a ground zone is in green, indicating to me that it is on the bottom copper layer. The IC and associated traces are in red, indicating to em that they are on the top copper layer. I don’t see anything that indicates to me that the ground zone is anything but continuous in that feature area you are referring to. Am I missing something?
Call them ‘small peninsulas’ instead if that helps.