Click on the cogwheel in the 3D-viewer and make sure to check ‘Show filled areas in zones’.
Filled areas in zones is checked. But if I uncheck ‘solder paste layers’ I can see my vias. So now I’m searching for solder paste layers and learn about them…
As far as I am aware KiCad does not even cater for thermal relief vias.
In your case everything is as it should be.
If there are vias in filled zones under a chip they would be covered by the paste layer in the 3D-viewer.
Vias in general have solid connections since they are not meant to be soldered on, except when present as part of filled zones under chips. Purpose here is to have a solid connection acting as a heatsink to the chip.
It is also a good idea to keep the paste patch under the chip rather smaller. Reason here is that too much paste makes the chip simply float, or even drift off. If the chip manages to just float high enough there will be hardly any connections to the pins, and the pain of fixing that mess sets in.
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Part of the confusion is terminology. You need thermal vias to get the heat away from the chip. The point emphasized by the data sheet you quote is that you shouldn’t use thermal relief in those vias. (To add to more confusing terminology, some people call them via thermals !). These are the webbings that attach a via to surrounding copper. Solid via means a solid connection, no webbings. (It is not about filling the via hole with solder).
And as Jos mentioned, when KiCad makes vias within a copper zone, it is solid by default.
You need those webbings – call them thermal relief, or via thermals, as you wish – when attaching through hole parts to largish copper zones or fat tracks. Makes your life less interesting while soldering and “even more” less interesting while desoldering. Attaching a picture so you get the idea.
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See also
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You have paste over the vias. Disable visibility of the paste layer and you will see the vias.
And regarding thermal vias in exposed pads: We typically make this inside the footprint using through hole pads of the correct size. These through hole pads would get the same pin number as the large pad. See Tutorial: How to make a footprint in KiCad 5.1.x? for a detailed tutorial and https://kicad.org/libraries/klc/F4.4/ as well as https://kicad.org/libraries/klc/F6.3/ for how it is applied to the official lib.
We have a footprint generator that makes footprints like these: https://github.com/pointhi/kicad-footprint-generator/tree/master/scripts/Packages/Package_Gullwing__QFP_SOIC_SO(documentation is in the process of being added https://github.com/pointhi/kicad-footprint-generator/pull/380) (There is also a similar generator for no lead packages in the same repo.)
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Thanks for the links!
One question: does the solder paste layer cover the vias during manufacturing?
Yes and no.
Depends somewhat how much and exactly where the paste needs to be without having the chip take off.
I can guarantee you that if you would cover the whole thermal pad with paste you will run into fab-issues. Especially with small VQFN’s and such. With too much paste the surface tension (during the reflow process, far worse with hand technics) may not be enough to actually pull down the chip.
Most application notes i have read regarding this suggest somewhere between 50 to 80% area coverage depending on stencil thickness, solder loss through vias, …
It is also a good idea to split up the paste pad for such a large pad as it better allows gases to escape and it also reduces the chances of paste being scoped out by the squeegee. (I personally aim for 1 to 1.2mm side length for these smaller pads.) All of this is explained in great detail in the tutorial linked above.
Exactly. I only scratched the surface. There is more, we have influences like room temperature, air pressure, moisture in the air and moisture on the board, dust, shape/tension within the board, surface, paste, the process how the paste gets onto the board. Did I miss something?
As for belly-pads, I always break them down in small patches. For SMD pads in general I take off at least 10% paste. 61.8% seems to be the best ratio.
It seems to be too precision information.
I think anything what was said was about how it should be done for normal automatic production.
The vias has to be no bigger then 0.3mm to not stole the paste during reflow soldering. The paste should be not too much to not make shorts to other pads.
I know (I have never done it myself) that amateurs who hand-solder such footprints do things differently. In such footprint there would be probably two vias in thermal pad big enough to solder to the thermal pad from backside. The thicker the PCB the bigger via is probably needed to see that you soldered successfully to thermal pad. I think such vias can have diameter of even 5mm if thermal pad is big enough.
This will give the IC the enough good thermal connection to GND copper at backside. It could be used in production I think, but it would need these vias to be hand soldered so would be more expensive.
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In that case just make it 60% 
I removed the vias and added pads of 0.5mm in the foot print. I’m not sure if I’m at 60% pad size for the paste area, but I did make it smaller. I submitted the boards yesterday for manufacturing.
Thank you everyone for the input! I’m not 100% with this area yet, but I have a better understanding.
Do we have a python wizard to quickly drawing this expose pad and where online ?
Yes see links above (part of the gullwing generator makes such a pad. If you do not need the full generator simply extract only that part.)
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Last time I remember that I have to use wizard to create a new footprint, and to copy and paste or text editor to move it into the existing footprint. Is this now get easier?
The thing i linked above is a standalone python script. It outputs a footprint as defined in its input files. (see documentation pull request also linked above for access to a preliminary documentation.)
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