Spice half bridge gate driver issues

Schematic Simulation (Ngspice)
1

Hi all,

I am reasonably new to KiCad and this is my first post here, so apologies in advance if I offend anyone with my ignorance.

I am building a circuit which ultimately connects to a full bridge (H bridge) output. The circuit as a whole works really well (MPPT charging a “battery”, triangle wave gen etc). However, I cant for the life of me get a gate driver to work. I have been to various websites (TI, Infineon, diode, to name a few), downloaded the spice model and created a footprint. Then I built a basic test rig (ideal supplies, MOSFET H bridge powering a load) and worked through the list of gate drivers (with datasheets in hand), but not one worked.

Now, I imagine the questions here may be “what was the error”, but really, there was a variety of errors, from the spice files not loading in to the symbol editor (saying something about expected lines) through to errors like “doAnalyses: TRAN: Timestep too small;”.

These are the components (gate drivers) I tried:
IRS2008S
2ED2109S06F
UCC27200
SM74104
UCC27714
LM5100A
IR2183
DGD2103M
UCC27524
UCC3895
TPS28225
IRS2302S

I was hoping that someone in the community could try any of the above and see if it works for them? I would love to know if I’m just doing something stupid.

Thanks

2

There is an example with 2ED2109 at Simulation examples for KiCad/Eeschema/ngspice - #4 by holger .

3

Hi holger,

Thanks for your reply. This is actually a really good example of my problem. This circuit is the reason I tried this gate driver, and before I installed KiCad 7.0.0-0, this circuit worked. Now if I run the circuit downloaded directly from the forum, it works if I just load it up and run it, however, the moment I open the gate driver symbol properties and look at the simulation model, I get the following warning: “Too many parameters for subcircuit type “2ed2109s06f” (instance: xxu1)
Error: there aren’t any circuits loaded.”

If I try to make my own symbol with the “2ED2109S06F_ng.lib” spice file, I get the following error: 2ED2109S06F_ng.lib:168:3: expected newline

I should say Im using a a Mac (dont judge me, its for work :).

Thanks for any further advice.

Edit: I have just run the 2ED2109S06F simulation on a PC with KiCad 6.0.11 on it and I am able to open the symbol, look at the spice code, then run it again just fine. So, it’s either a version or OS thing I guess.

4

Just to confirm, it is the version, not the OS. Works fine on 6.0.11, not 7.0.0 or 7.0.1

5

Generally speaking, when simulating half bridges or power supplies, the voltages are higher than with low power circuits or even ICs. Then it is useful to relax the precision requirements for op and tran simulations by adding suitable options, e.g.
.options chgtol=1e-11 abstol=10p reltol=0.01 vntol=10u
often also the integration method GEAR delivers results when default TRAP fails.
.options method=gear

Simulation models are mostly made without ngspice in mind. Infineon models always need some modifications, other sometimes.

6

Hi, yes, thank you. I do relax a lot of precision, and it works in 6.0.11, so I’m happy. It’s a little bit of a bummer that 7.0.0 and 7.0.1 dont work for this, because I love many of the spice related updates between V6 and V7 of KiCad. However, I’m sure it’ll all come right.

7

I find that the spice model of the gate driver DGD0506 offered by DIODES works well in 6.0.11.

image
image1813×843 14.6 KB

You can download the model and try it.
Search Results (diodes.com)

8

The simulation result

image
image1920×1025 46.9 KB

9

https://ltwiki.org/files/LTspiceIV/Vendor%20List/
Index of /Spice_Model_CD/Vendor List

Here is a my own custom collection of spice models
and tools to help.

elechlp.zip (669.5 KB)

One of the major causes of ‘time step too small’ in
ngspice is an incompatible spice model parameter.

As ngspice parses through the circuit and reads
the spice models it will attempt to debug a
non-readable parameter entry and upon fail will
‘step over it’ to the next model resulting in a
‘nyquist’ equation that blocks successful simulation.

I also advise removing all comments preceded by the
typical “*” asterisk in any given spice .mod model,
.sub subcircuit and especially .lib library files.
This information can be as extensive as this post
and although it is ‘escaped’ by the comment feature
ngspice still has to step over it to continue.

As you may have noticed, when using large capacitance
such as for filtering power supply output there can
be a significant delay in loading time and I usually
have to set the transient pre-start time up to 500ms-1s
to allow for the circuit to full load before simulation.
Otherwise this also results in ‘time step too small’ readout.

I found this …

* MAX5064A MACROMODEL
* ----------------------------
* Revision 1.0 3/2005
* ----------------------------
* The MAX5064A is a high speed, 125V, half-bridge n-channel MOSFET driver
* which can source and sink upto 2A peak.
* ----------------------------
* Connections
*       1  = BST 
*       2  = DH
*       3  = HS
*       4  = AGND
*       5  = BBM
*       6  = IN_H-
*       7  = IN_H+
*       8  = IN_L-
*       9  = IN_L+
*       10 = PGND
*       11 = DL
*       12 = VDD
*-----------------------------
*$
**************************************************
.SUBCKT MAX5064A 1 2 3 4 5 6 7 8 9 10 11 12 
**************************************************
*UVLO VDD(7.3V and 500mV hyst)
VUV 14 4 7.3V 
GUV 4 15 POLY(2) 12 14 15 4 0 1M 500U
DUV2 4 15 DA
CUV 15 4 1P
DUV1 15 16 DA
VUV1 16 4 1V
***************
*UVLO BST(6.9V and 500mV hyst)
VUVA 17 3 6.9V 
GUVA 4 18 POLY(2) 1 17 18 4 0 1M 500U
DUV2A 4 18 DA
CUVA 18 4 1P
DUV1A 18 19 DA
VUV1A 19 4 1V
***************
RAGPG 4 10 1G
RHSAG 3 4 10MEG
CIN1 6 4 2.5P
CIN2 7 4 2.5P
CIN3 8 4 2.5P
CIN4 9 4 2.5P
***************
*IN_L+ (VDD/2 and VDD/6.6 hyst)
EVDD1 20 4 12 4 0.55
GINA 4 21 POLY(3) 9 20 21 4 12 4 0 1M 0 0 0 0 0 0 150U
DINA1 4 21 DA
CINA 21 4 1P
DINA2 21 16 DA
***************
*IN_L- (VDD/2 and VDD/6.6 hyst)
EVDD2 22 4 12 4 0.4
GINB 4 23 POLY(3) 22 8 23 4 12 4 0 1M 0 0 0 0 0 0 150U
DINB1 4 23 DA
CINB 23 4 1P
DINB2 23 16 DA
***************
*IN_H+ (VDD/2 and VDD/6.6 hyst)
EVDD1H 24 4 12 4 0.55
GINAH 4 25 POLY(3) 7 24 25 4 12 4 0 1M 0 0 0 0 0 0 150U
DINA1H 4 25 DA
CINAH 25 4 1P
DINA2H 25 16 DA
***************
*IN_H- (VDD/2 and VDD/6.6 hyst)
EVDD2H 26 4 12 4 0.4
GINBH 4 27 POLY(3) 26 6 27 4 12 4 0 1M 0 0 0 0 0 0 150U
DINB1H 4 27 DA
CINBH 27 4 1P
DINB2H 27 16 DA
***************
*AND1
EAND1 28 4 15 4 1
EAND2 29 4 21 4 1
EAND3 30 4 23 4 1
DAND1 31 28 DA
DAND2 31 29 DA
DAND3 31 30 DA
RAND1 16 31 1MEG
***************
*AND2
EAND1H 32 4 18 4 1
EAND2H 33 4 25 4 1
EAND3H 34 4 27 4 1
EAND4H A34 4 15 4 1
DAND1H 35 32 DA
DAND2H 35 33 DA
DAND3H 35 34 DA
DAND4H 35 A34 DA
RAND1H 16 35 1MEG
***************
*PROP DELAY1
EPR 36 4 31 4 2
RTL1 36 37 1K
T1 37 4 47 4 ZO=1K TD=25N
RTL2 47 4 1K
***************
*PROP DELAY2
EPRH 39 4 35 4 2
RTL1H 39 40 1K
T1H 40 4 48 4 ZO=1K TD=25N
RTL2H 48 4 1K
***************
*BBM PIN
VBBM 42 4 1.3V
DBBM2 42 45 DA
RBBM1 45 5 10K
FBBM3 4 46 VBBM 1
IBBM3 4 46 4.482U
DBBM3 46 16 DA
DBBM4 4 46 DA
EBBM2 49 4 46 4 1
DBBM5 49 50 DA
RBBM5 50 4 10K
***************
*BBM_L
EBBM1 38 4 47 4 1
DBBM1 43 38 DC
RBBM2 38 43 2MEG
FBBM1 43 38 VBBM 1
CBBM1 43 4 2.29P
GBBM1 38 43 50 4 1M
***************
*BBM_H
EBBM1H 41 4 48 4 1
DBBM1H 44 41 DC
RBBM2H 41 44 2MEG
FBBM1H 44 41 VBBM 1
CBBM1H 44 4 2.29P
GBBM1H 41 44 50 4 1M
***************
*OUTDRV_L
VO1 51 4 0.5V
GOL1 4 52 POLY(2) 43 51 52 4 0 11M 1M
DOL1 4 52 DC
DOL2 52 16 DC
COL1 52 4 1P
***************
*OUTDRV_H
GOH1 4 53 POLY(2) 44 51 53 4 0 11M 1M
DOH1 4 53 DC
DOH2 53 16 DC
COH1 53 4 1P
***************
*OUTPUT_L
EMDR 54 10 POLY(2) 16 52 12 4 0 0 0 0 1
MP1 11 55 12 12 MP1 L=0.5U W=0.379M
MN1 11 56 10 10 MN1 L=0.5U W=0.188M
CGS1 55 10 10P
CGS2 56 10 10P
RG1 54 55 40
DG1 54 55 DB
RD2 54 56 40
DG2 56 54 DB
CLIN 11 10 1P
****************
*OUTPUT_H
EMDRH 57 3 POLY(2) 16 53 1 3 0 0 0 0 1 
MP1H 2 58 1 1 MP1 L=0.5U W=0.379M
MN1H 2 59 3 3 MN1 L=0.5U W=0.188M
CGS1H 58 3 10P
CGS2H 59 3 10P
RG1H 57 58 40
DG1H 57 58 DB
RD2H 57 59 40
DG2H 59 57 DB
CLINH 2 3 1P
****************
*ISUP
ISUP1 12 4 120U
ISUP2 1 3 15U
MP2 60 55 12 12 MP1 L=0.5U W=100U
MN2 60 56 10 10 MN1 L=0.5U W=50U
CL1 60 10 600P
MP2H 61 58 1 1 MP1 L=0.5U W=100U
MN2H 61 59 3 3 MN1 L=0.5U W=50U
CL2 61 3 600P
***************
DBTSP 12 1 DD
**************************************************
.MODEL MP1 PMOS(VTO=-0.7 KP=50E-6)
.MODEL MN1 NMOS(VTO=0.7 KP=100E-6)
.MODEL DA D(IS=100E-14 N=1M)
.MODEL DC D(IS=100E-14 N=1M RS=1)
.MODEL DB D(IS=100E-14)
.MODEL DD D(IS=0.5P RS=200m N=1 Cjo=28.43p)
**************************************************
.ENDS
10

Hello. In KiCAD 8, how to do I modify the netlist to insert options like this? Or were can I find a menu to choose integration or change other options? I’d searched the docs and this forum. Thanks.

.options chgtol=1e-11 abstol=10p reltol=0.01 vntol=10u
often also the integration method GEAR delivers results when default TRAP fails.
.options method=gear

11

Please do not occupy on old thread. Open a new thread with an appropriate title, so other users may benefit.

12