Spice and KiCad


#41

I noticed and got surprised by this too, when simulating the following curcuit:


using the corresponding BJT models from
http://robustdesignconcepts.com/files/pspice/libs/bipolar.lib

I had simulation results for the PNP BJT base in the kV range. The result seems to depend on the simulation step duration too. Running the simluation for 3s with different step durations:

  • With 1ms step duration I get 150kV overshoot
  • With 10us step duration I get 28V overshoots
  • With 1us step duration I get no overshoots (result is always in the expected 0-8V range

The problem with shorter step durations are simulation time (understandable) and GUI slowdown for zooming and panning.

As a comparison with a Spice based Windows circuit simulator for the same circuit simulation I get the expected result without overshoots with a 1ms step duration. I’ll try to track down the reason for the difference with the .listing trick someone pointed to here earlier.

I’m a newbie with simulation and Spice/KiCad in particular; could someone explain the reason for this behavior and if there is a way to resolve it (besides short step durations which make the GUI slow)?

Btw, thanks to the Cern team for this new simulation feature, I’ve been long looking for an integrated simulator I could run on Linux.


#42

Can you zoom-in on the Windows result & check the actual step used ?
(some allow you to see the spice points)

I believe some Spice’s use dynamic steps sizes,and probably also ‘protect users from themselves’ by not taking too much notice of very large values.
eg I’d never set a 1ms step size.
Spice relies on the next-result being not too far from the last one, which is why sub micro-second steps sizes are more usual for good sim results.
Of course, depends on the design, but astable designs have ‘sharp corners’.


#43

Yes, you were right:
with 1ms step size the spice point size is 1us
with 1us step size the spice point size is 0.1us
with 0.1us step size the spice point size is 0.01us
So it seems the spice point size is min(1us, step_size/10)

So this pretty much explains it, since I get good results with KiCad/1us too. Again the reason I used 1ms is speed. The Windows tool is much faster to run the simulation/plot drawing and the GUI more responsive during zooming with the same spice point size. I get comparable results with KiCad/1ms step size. Any idea for the reason for that? One thing I noticed is that the Windows tool seems to be multi-threaded (using 4 threads on my box), not sure about ngspice. [Edit: trying to limit it to 1 thread doesn’t make a difference, and I’m using Linux/Wine in any case which seems to use only a single core.]

Here are the Windows logs/simulation settings I could find, if they are of any help:
#logs/netlist:
R1 N001 N003 60k
R2 N003 0 5.6k
R4 N004 0 50
V1 N001 0 8
C1 N004 N003 22µ
Q1 N002 N003 0 0 PN2222A
Q2 N001 N002 N004 0 PN2907
.model NPN NPN
.model PNP PNP
.lib standard.bjt
.tran 0 100m 0 1u uic
.end

#logs/spice:
Per .tran options, skipping operating point for transient analysis.

Date: Sun Mar 19 23:45:47 2017
Total elapsed time: 2.096 seconds.

tnom = 27
temp = 27
method = modified trap
totiter = 200161
traniter = 200161
tranpoints = 100064
accept = 100056
rejected = 8
matrix size = 9
fillins = 4
solver = Normal
Matrix Compiler1: 886 bytes object code size 0.7/0.5/[0.5]
Matrix Compiler2: off [0.5]/0.5/2.5

#settings/compression:
ASCII data files: N
Only compress transient analyses: Y
Enable 1st Order Compression: Y
Enable 2nd Order Compression: Y
Window Size(No. of Points): 300
Relative Tolerance: 0.0025
Absolute Voltage tolerance[V]: 1e-005
Absolute Current tolerance[A]: 1e-009

#settings/Save Defaults:
Save Device Currents: Y
Save Subcircuit Node Voltages: N
Save Subcircuit Device Currents: N
Don’t save Ib(), Ie(), Is(), Ig(), or Ix(): N
Save Internal Device Voltages: N

#settings/SPICE:
Default Integration Method: modified trap (other options: trapezoidal, Gear)
Default DC solve strategy:
Noopiter: N
Skip Gmin Stepping: N
Engine:
Solver: Normal (other option: Alternate)
Max threads: 4
Matrix Compiler: object code (other options: (off), pseudo code)
Gmin: 1e-012
Abstol: 1e-012
Reltol: 0.001
Chgtol: 1e-014
Trtol: 1
Volttol: 1e-006
Sstol: 0.001
MinDeltaGmin: 0.0001
Accept 3K4 as 3.4K: Y
No Bypass: Y


#44

I took 15 minutes to build this circuit in LTSpice. I’m certain LTSpice uses dynamic step sizes, because occasionally it’ll abort a simulation with a squawk about “step size too small”. I don’t think the user has control over the minimum step size (maybe it’s buried deep in some “Options” menu), but it DOES allow you to set a ceiling (maximum) size for the steps. At any rate . . . after 15 minutes of playing with maximum step sizes, transistor models, and capacitor parasitics, I couldn’t make this circuit misbehave. I COULD slow the program to a crawl by limiting the maximum step size to 1 uS or so. I don’t think the program is sanitizing the results by removing unreasonable values, either.

I think I can get information about the actual step sizes being used by looking at the raw data files. Maybe I’ll do that when I have more time.

Mostly, I’m saying that there ARE alternative choices for low-cost circuit simulation.

Dale

p.s. - I should also add that the circuit seems to oscillate only for potentiometer settings between roughly 50K and 75K ohms, and this is dependent on supply voltage and transistor parameters. Circuit is probably more of a curiosity than something with significant commercial value.


#45

The circuit is just for curiosity, I saw it somewhere and simply wanted to understand how it works. I found KiCad’s tuning feature especially useful for this. The idea to integrate it with the rest of EDA tools is great too, switching between applications to design the circuit/ simulate it is not practical especially for a newbie like me. I don’t know of a good open source alternative and I don’t like having to start Wine for this.


#46

Full disclosure: I have no monetary or personal connection to Linear Technology (now Analog Devices) but I am sold on LTSpice as a simulation tool. Except for its library system (And where have we heard similar caveats?) it pretty much beats the pants off any other SPICE tool I’ve used.

LTSpice is definitely NOT open-source; it’s about as proprietary as you can get. However, it IS a no-charge giveaway from a respected major corporation who make no apologies for their motives. They hope that LTSpice, with the simulation models of their products, will convince you to incorporate their products into your designs.

I know there are versions available for Windows and Mac. I’m not sure about Linux/Unix. And yes, switching to or from LTSpice to any other EDA tool is a pain - the commands, menus, shortcut keys, drawing tools, etc, all work differently. Write it off as a “character building exercise”.

Dale


#47

There is also QUCS (http://qucs.sourceforge.net) which is very capable and runs on all platforms. As @dchisholm says, LTSpice is the defacto standards as it has the best support and range of models available. Simulation is probably more useful in part of a circuit than the whole schematic anyway.


#48

Hi,

I spent some time putting together a simulation for a constant current source. My aim being to be able to measure the current for different designs. However it seems to be impossible to show current signals in the simulator. In fact current sources don’t seem to work either. This could just be me not understanding how to use it - it took me the better part of a day to become familiar enough with it to actually get anything working at all.

Will support for this be added?


#49

For those with an enduring relationship with LT-Spice, LT-Spice circuits can be converted to gschem compatible schematics with

provided custom schematic symbols are used.

These can then be exported as netlists to gEDA PCB, pcb-rnd, or even to KiCad with the right exporter. gschem also supports multiple pathways for exporting to various FOSS spice tools.

Another approach for LT-Spice users is to import the LT-Spice netlist directly into pcb-rnd, but this requires a bit of LT-Spice netlist and/or library hacking due to the lack of attribute options available for components in LT-Spice

With either approach, once the netlist +/- layout is laid up in pcb-rnd, pcb-rnd can export a KiCad layout.

QUCS lacks a distinct “component” that can be easily converted, but translate2geda does a reasonable job of converting a QUCS schematic into a gschem compatible one, provided that the necessary, custom schematic symbols are used.

Based on recent impressions/comments, the QUCS project seems disinclined to facilitate export to PCB layout tools (in general, not just gEDA PCB / pcb-rnd) by regularizing or simplifying their component descriptions at this point in time, which is a shame. Perhaps if the KiCad people approached them as well, they might be willing to reconsider.

Cheers,

Erich.