[Solved] Simulation issues with MOSFETS

Schematic Simulation (Ngspice)
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I’m brand new to the simulation, and fairly new to Kicad, so please excuse any breaches of protocol.

I have the following high voltage MOSFETs to push and pull charge to/from the capacitor. The simulation looks great when the upper rail is 20V, but at 30V and above, the transistors do not turn off completely.

Both of these parts are 60V max Vds. Vgs max is +/- 20. So my question is, is the problem of the model breaking down at higher supply likely a limitation in the spice model of the part? If the answer is yes, that just about does it. I realize there are better places to ask this question, but I don’t know where they are.

I’m using Kicad 7.0 via Flatpak on Ubuntu 22.04

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Could not include both images in first post.

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If I understand correctly, I think that those current spikes are going into and out of your 1 uF Capacitor. It looks to me like the current goes to zero between the spikes.

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That is correct. After the cap is charged or discharged, MOSFET has done it’s job. You can’t even tell when it would have cut off. The traces shown are exactly what I want.

The problem is when the rail is increased, the P channel does not shut off completely, and the higher the voltage, the worse it gets. I’m trying to model a 40V rail, but things start to go sideways between 25 and 30, and get worse.

The sine inputs are for convenience in modelling. That’s not going to be how they are driven.

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Yes OK thanks. That all makes sense. I have not used NGSpice, but I think that on this forum I have encountered a number of complaints about models; I think for MOSFETs.

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What spice models are you using for your transistors?

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They are the ones available on Mouser from componentsearchengine.com.

Here is the p-channel. The preable indicates it is created by the manufacturer.

*---------- DMP6185SK3 Spice Model ----------
.SUBCKT DMP6185SK3 10 20 30
*     TERMINALS:  D  G  S
M1 1 2 3 3 PMOS L = 1E-006 W = 1E-006 
RD 10 1 0.03231 
RS 30 3 0.001 
RG 20 2 16.84 
CGS 2 3 7.103E-010 
EGD 12 30 2 1 1 
VFB 14 30 0 
FFB 2 1 VFB 1 
CGD 13 14 6.5E-010 
R1 13 30 1 
D1 13 12 DLIM 
DDG 14 15 DCGD 
R2 12 15 1 
D2 30 15 DLIM 
DSD 10 3 DSUB 
.MODEL PMOS PMOS LEVEL = 3 U0 = 400 VMAX = 1E+006 ETA = 0.001 
+ TOX = 6E-008 NSUB = 1E+016 KP = 30.52 KAPPA = 19.32 VTO = -0.9885 
.MODEL DCGD D CJO = 2.071E-010 VJ = 0.8 M = 0.6 
.MODEL DSUB D IS = 1.567E-009 N = 1.266 RS = 0.05804 BV = 25 CJO = 3.071E-011 VJ = 0.8 M = 0.6 TT=1.1E-08
.MODEL DLIM D IS = 0.0001 
.ENDS
*Diodes DMP6185SK3 Spice Model v1.0M Last Revised 2018/2/1
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Please zip your project from above (including all models used) and post it here. I will have a look then.

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I just had a look at the Diodes model, directly downloaded from the companies web pages at Spice Models. There is a bug in the model of DMP6185SK3 in line
.MODEL DSUB D IS = 1.567E-009 N = 1.266 RS = 0.05804 BV = 25 ...
This term is to describe the intrinsic reverse diode of the transistor. The parameter BV = 25 is to set the breakdown of the diode, which is probably wrong for a 60 V device. If you change it to BV = 65 , it should be o.k. then.

However watch the peak current in your circuit, which exceeds the allowed data sheet value by a factor of two?

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That looks like it fixed the issue. Thanks for your help. There are a lot of unfamiliar numbers in the MOSFET model.

About the peak current - I know if it’s not listed it’s not there, but the pulsed current is spec’d for 10uS. Those spikes are much shorter. At this time I don’t know what the real capacitive load is, so there may be some major changes. Also there may be some current limiting on the path to the load.

Thanks again!

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