[SOLVED] OpAmp-based logic level tester in ngSpice

Hello!

I am struggling with simulating the attached circuit in ngSpice. It is meant to be a logic level tester, so when the voltage is above a certain threshold (set by the potentiometer midpoint VBIAS), it would light up an LED. However, OpAmp U1 (LM324) seems to switch regardless of the voltage on its inverting input. Since I am new to KiCad, I am not sure if I got the right SPICE model for LM324 (and I found it by googling anyways). Could anyone who can code in SPICE help me understand if I have a mistake in my model definition, the element definition or, in fact, a bug in the circuit? Thanks!

I would love to upload the files, but the forum would not let me do so.
In this plot: green = VPROBE; red = I_d (LED_GREEN); blue = VBIAS.

SPICE model is listed below.

lm324.lib
* BEGIN SPICE MODEL LM324

.SUBCKT LM324_ED OUT1 IN1M IN1P VCC IN2P IN2M OUT2 OUT3 IN3M IN3P VEE IN4P IN4M OUT4 

* have to match order in model below: +IN -IN +V -V OUT
X1 IN1P IN1M VCC VEE OUT1 LM324
X2 IN2P IN2M VCC VEE OUT2 LM324
X3 IN3P IN3M VCC VEE OUT3 LM324
X4 IN4P IN4M VCC VEE OUT4 LM324

* ON SEMICONDUCTOR NEXT GEN MODEL 9/27/2018
* MODEL FEATURES INCLUDE OUTPUT SWING, OUTPUT CURRENT
* THROUGH THE SUPPLY RAILS, CLASS B OUTPUT STAGE, OUTPUT
* SWING, OPEN LOOP GAIN AND PHASE WITH RL AND CL EFFECTS,
* POWER SUPPLY REJECTION WITH FREQUENCY EFFECTS, COMMON
* MODE REJECTION WITH FREQUENCY EFFECTS, INPUT VOLTAGE
* NOISE WITH 1/F, INPUT CURRENT NOISE, INPUT BIAS AND
* OFFSET CURRENT, INPUT COMMON MODE VOLTAGE RANGE, VOS
* WITH TEMPERATURE EFFECTS, AND QUIESCENT CURRENT WITH
* TEMPERATURE EFFECTS.
* MODEL TOTAL SUPPLY VOLTAGE RANGE IS 3 TO 36 V.
* MODEL TEMP RANGE IS -55 TO +125 DEG C.
* NOTE THAT MODEL IS FUNCTIONAL OVER THIS TEMP RANGE
* BUT NOT ALL PARAMETERS TRACK THOSE OF THE REAL PART.
* NOTE THAT LIKE THE REAL PART THERE IS NO AB BIAS
* IN THE OUTPUT STAGE WHICH UNDER SOME CIRCUMSTANCES
* CAUSES HIGH OUTPUT IMPEDANCE AND OR CROSSOVER DELAY
* WHICH CAN EFFECT THE PERFORMANCE IN SOME CIRCUITS.
* THE COMBINATION OF OUTPUT CURRENT SINK AND NO AB
* BIAS WHEN USED WITH A LARGE CLOAD CAN CAUSE SOME
* INTERESTING SMALL SIGNAL STEP OVERSHOOTS THAT ARE
* LARGER THAN NORMAL AND RAMP LINEARLY RATHER THAN
* BEING SHAPED LIKE A CLASSIC OVERSHOOT. THIS HAPPENS
* IDENTICALLY WITH THE REAL PART AND THE MODEL.
*
* PINOUT ORDER +IN -IN +V -V OUT
* PINOUT ORDER  1   2   3  4  5
.SUBCKT LM324 1 2 3 4 5
R44 4 6 4E4
I1 4 7 0.5E-6
Q1 4 8 9 QPI
Q2 4 2 10 QPA
Q3 9 9 11 QPI
Q4 10 10 11 QPI
Q5 12 13 4 QNQ
Q6 13 13 4 QNQ
Q7 4 12 14 QPQ
Q8 3 14 6 QNQ
Q9 15 6 4 QNQ
Q10 3 15 16 QNQ
Q11 3 16 17 QNQ
R67 17 16 4E4
R68 5 17 18
Q12 4 15 5 QPQ
Q13 15 17 5 QNQ
I2 18 3 120E-9
I3 19 3 60E-9
I4 20 3 1E-6
Q14 11 18 3 QPQ
Q15 14 19 3 QPQ
Q16 5 7 4 QNQ
Q17 15 20 3 QPQ
C15 21 22 4.8E-12
R69 12 21 3
R70 12 15 3E9
E2 23 8 3 0 -10E-6
V51 23 1 1.56E-3
I6 3 4 5E-6
R71 4 3 4.5E5
Q18 12 9 11 QPQ
Q19 13 10 11 QPQ
C17 12 13 8E-12
C18 6 15 1E-12
C21 3 24 100E-15
R78 11 24 3E5
C22 1 2 0.23E-12
C23 2 0 0.79E-12
C24 1 0 0.79E-12
E3 22 0 15 0 2
C25 5 0 50E-15
Q20 25 25 0 QNQ
G1 3 4 VT 0 3E-4
I7 0 25 1E-3
V53 25 26 0.25
R79 0 26 1E6
E4 VT 0 27 26 1
R80 0 VT 1E6
V54 27 0 0.55
R81 0 27 1E6
.MODEL QPQ PNP IKF=3E-3 RC=300 KF=4.8E-17 BR=1
.MODEL QPA PNP IKF=3E-3 RC=380 IS=1.01E-16 VAF=245 RE=5 RB=1700 BF=300 KF=4.8E-17 BR=1
.MODEL QPI PNP IKF=3E-3 RC=380 IS=1.01E-16 VAF=290 RE=5 RB=1700 BF=306 KF=4.8E-17 BR=1
.MODEL QNQ NPN IKF=5E-3 RC=25  KF=4.8E-17 BR=1
.ENDS
* END SPICE MODEL LM324

.ENDS LM324_ED

This forum has a bunch of automated features to reduce the workload for moderators to prevent spam. I believe the most severe restrictions on uploading files & multiprle screenshots are lifted after you’ve accumulated half an hour of “viewing time”.

About your schematic:
My first guess is that the potetiometers do not work properly. As far as I know this is not supported and you have to use two separate resistors (There is a way to change the value of a resistor “on the fly”, but simulation of a real potentiometer needs a few lines of script.

OK, I guess, I’ll have to wait a couple of days before I can upload the files.

Regarding your comment on potentiometers: I use the following model

pot.lib
.SUBCKT pot_lin 1 2 3 r=100k k=0.5
*
R1 2 3 {r*(1-k)}
R2 1 2 {r*(k)}
.ENDS

I am uncertain of the design intent but I think it may be a bad design. I am focused on the source impedance of the wiper of RV1. You will get some voltage division between TEST1 Vsource driven through R1, and the source impedance and source voltage from RV1. When RV1 is set to midpoint, its driving impedance will be 25% of the potentiometer resistance end to end. When RV1 is set to minimum or maximum, its source impedance will ideally be zero. The curve could be analyzed algebraically but I would do best using a spreadsheet. I suspect that you want another op amp section as a unity gain follower for RV1. Then put a resistor > 2K ohms in series with that output. You would probably increase R1 to 2K ohms up to 10K.

Thanks for the feedback. I was aiming for a tester that could cover a wide range of logical levels (e.g., TTL, RSR-232, etc), so I wanted to make the voltage levels at both inputs adjustable in a wider range. For instance, the logical voltage levels for RS-232 are actually negative.
So, all the RVn serve this purpose: keep the inputs easily adjustable. I am sorry, but I did not quite get your idea of putting a unity gain OpAmp here. Is it for noise isolation?

One more thing: isn’t it surprising that in the plot above there is some current flowing through the green LED? VBIAS > VPROBE always, but yet the OpAmp switches. I do not understand the reason why.

Could you plot VCC and the output of OpAMP1?
And… What are the values of the current and voltage sources?

Sure: red = VCC; green = pin 1 of U1
plot_1

VTest is a sine voltage source
plot_2

OK, so I can finally upload the project files. Here they are

logic-level-tester.sch (12.9 KB) lm324n.lib (2.6 KB) pot.lib (75 Bytes) bc107.lib (768 Bytes)

I agree with BobZ - this design will cause problems. If RV1 is towards one of its extremes, you will be connecting Vcc, or GND, via a 1k resistor to the circuit under test, which in many (most?) cases will interfere with the voltage you are monitoring and possibly put the circuit under test into a fault state.

I think you need to buffer the input VSOURCE with a unity-gain op-amp so your tester presents a very high, or effectively infinite, impedance to the circuit under test.

With the circuit as shown: The p-p signal at VPROBE will be maximum when RV1 is at center and it will reduce towards 0 as you adjust RV1 towards either end. You could simply make R1 = 20K and add 20K in series with RV1 wiper. This assumes that RV1 is a low value potentiometer such as 1K. That would be less perfect but might be close enough. Using a low value (such as 1K at RV1) will draw significant mA from Source1; maybe that is OK.

My purpose in the op amp following RV1 is to first have a known low output impedance for RV1-voltage, and pass that through a series resistor so that you have a known series impedance. Also it allows you to increase the value of RV1 so that it might be drawing microamps from SOURCE1 instead of milliamps. I am assuming that SOURCE 1 is maybe 5V to 24V DC.

What is this tread about?
I first thought it was about getting spice working with an Eeschma schematic, but the squarewave of the second post suggests that the spice simulator is working.

Is it about designing a circuit?
At first I did not look at the schematic at all. Just saw a potentiometer, which triggered a memory of these things having problems with Eeschema + ngSpice.

To me it looks like a “mess of wires”
It took me a few minutes to realize that the inputs of U1A and U1D are both parallel. Which means you have an unused opamp (in disguise) and you can use that to make a proper voltage bufffer.

I have not bothered to look at when which led switches, as I do not know your intention.

You can use a trick of putting leds in series and then connecting an OpAmp output to the node in between. This way you can light up one of the LED’s depending on the output state of the opamp.

Aahrrg… U1B and U1C also have their inputs paralleled, so you have only 2 opamps in actual use, except maybe for Q1, which I have not looked at.

My advise is to start with a buffer, then a single comparator, and get that to work in spice, and also on a breadboard (I’m an old fashioned guy, like to see and touch things). After that slowly extend functionality and experiment a bit. Before you’re halfway the complete circuit, you should also have a description and something similar to a Karnaugh_map of when which led switches, and at what voltage levels, and use that to fill in the last details.

:slight_smile: Yes indeed. Consistent with your overall point: I should mention that I do designing much better than I do reverse engineering. And although there seems to be some sense to the op amp inputs, I guess I am unsure of the overall circuit function. Recently I have been struggling to figure out a (preliminary) circuit which I designed maybe a year ago. To put this in perspective, I have designed many circuits which worked as intended “out of the box” but reverse engineering is just more of a struggle. Good point about the redundant op amp. Another thing is that the op amps are mostly being used really as comparators and I am tempted to say that the design should use an LM339 quad comparator instead of an LM324 op amp. But the LM324 output can both source and sink current, and more current than the LM339 so perhaps I should not argue the point about using the LM339.

But…I think the best approach would be to first define the desired function and start with a clean “sheet of paper”; do a new design. I am not 100% certain but this design reminds me of many poor ones which I have seen. Your point of the redundant op amp supports that theory.

The simulation is correct. You’re operating the opamp above its input common mode voltage range. Its output is undefined under such conditions.

See section 2.4 in https://www.ti.com/lit/an/sloa277/sloa277.pdf.

I see. Indeed, a valid point. But then there’s the problem mentioned below: the voltage at the OpAmps inputs should never get below the common ground, which will happen if I just connect it to an RS-232 line (logical “1” is somewhere between -4…-8 V). Hence, I have RV1,2 to accommodate such voltages and make sure it is always within valid range.

However, I may add another resistor to RV1 to reduce the current drain. Thanks for the thought!

Yes, but that is not the case in this simulation (consider the plots, VPROBE, VBIAS > 0). I have RV1,2 to prevent the voltage dropping below the ground level.

Thank you for the comments, I will consider them.

If it is not yet clear, the question is:

Why does the OpAmp switch even though the voltage at the non-inverting input is ALWAYS higher than on the inverting input?

You can observe this in the plots. And I suspect my SPICE model is wrong. But I do not know SPICE. That’s it.

OK, it is just a toy circuit that I use to understand the software. I wanted to make use of all the 4 OpAmps in LM324 and learn how the simulation works.

Now, why LM324? Answer is, because I have a bunch of them. And I can use them as comparator. Might not be the best choice for this, but it should work for this purpose.