[Solved] Creative multi-part footprints (and drc errors)

I am not asking for footprints – I build my own and have hundreds. I understand how to do all the garden-variety stuff, but I have some footprints that are just odd, or I designed to fit multiple devices for procurement flexibility, and have drc errors I would like to not have happen.

So these two footprints are simple enough to make by adding pads with the same number, and they route just fine and DRC is happy:

And even this x2y cap, with overlapping ground pads (need two for schematic) is just fine and no drc errors (even though I kinda expected errs):

But then I do something simple like an 0603 jumper with a copper short, and drc errors. It needs to be different pad numbers for the schematic. This fp works, it just throws drc errs.

Or this combo soic/vssop I need for opamps that may be in either package (and I am lucky to get either these days with the supply chain). DRC really hates the vias and traces (but it routes and works well). If I use smt pad rectangles I can hack around the trace errors, but maybe there is a better way:

Anyone have some insight? thx, gil

1 Like

For your jumper, you can have a look at KiCad’s “solderjumper” library.

They use a graphic polygon, and to make DRC happy they rely on an old hack in KiCad that uses the “net tie” keywords. Here a screenshot from: Footprint Editor / File / Footprint Properties of such a footprint:

The “net tie” hack will be improved upon in some future kicad version, but it has been postponed a few times.

For the soic / vssop combination there is also no better solution that I know of. “Design blocks” would be an excellent solution for this, but that is also not yet supported by KiCad.

Creating the short tracks and via’s from extra pads SMT and THT pads is one of the very few options. If you do this, then be aware of the solder mask and paste layers of those “copper tracks”.


You think like me!! Here is my SOT-23/SOT-223 combi. I cannot tell you whether I have gotten DRC errors. I guess I have learned to ignore a lot of those…

1 Like

yeah, nice bobz.
I first did this years ago when a part was available in soic16 150mil or 300mil bodies:

And an FFC that would let me use 10 or 12 pin sockets:

A limor fried design inspired an edge-SMA or U.FL connector (can’t really see where the u.fl fits, but it drops on the pads):

Even a simple idea I ran across at sparkfun is handy: toggle offset header pads a few mils for retention during soldering (on two-row headers just scootch the four corner pins out):


I like that one! As long as you can insert the connector.

For hand soldering (most of what I do) I am accumulating a library of footprints with fat corner pads. It really helps significantly. Here is my MSOP-8-Bigfoot2


bigfoot – funny. Soldering could be an entire thread, and maybe not appropriate for this forum, but I regularly hand solder down to 0.5mm pitch, and yeah, tacking the corners is a critical first step.

Rather than trying to hold a part’s position with tweezers or fingers when tacking a corner, a trick I use is a bit of scotch tape – stick it down on the part leaving pins on one side exposed, then grab the ends of the tape, fine-tune position to the pads, and stick the two ends to the board. The part is now not going anywhere. Check position with a loupe or such (repeat alignment as needed) and then tack a corner or two. Peel tape off and tack other side.

I have done many chips by just soldering a complete blob on all the pins on one side and using (good) solderwick to suck it off. I also have good luck by oozing a bead of flux on the pins and using an angled-flat tip loaded with solder and wiping across the whole row in one motion, many times with no shorts to wick off. Works well for any gull wing part. I have even done m.2 sockets and hdmi jacks that have exposed pins.

I also use a stencil and paste for some protos – after loading them up I fry them, er, reflow them, on an electric griddle.

A white plastic eraser is great for cleaning oxide off hasl pads on the board first but I usually get immersion gold since the chips sit much flatter and solder better.
OK, guess I have ranted enough for now :slight_smile:


A product I often use, rather than scotch tape, is “blue tac”.
It must be available world wide, probably with many trade names. Here are some examples:

Use one or two small pieces strategically placed while initially soldering a couple of pins. The beauty of this stuff is it is still easy to adjust components. It lifts without leaving a residue, as long as you don’t leave it on the PCB for a week, and is reusable.
Keep the hot iron tip off the stuff though!

Not a brilliant idea with reflow however! :-1:

1 Like

Hmm, tack sounds interesting @jmk.

And @paulvdh, that “net tie” hack works well. I presumed keywords were there as a search term convenience not a super-double-secret-tunnel to get code words to the software :slight_smile:

For my simple jumper (which I like when I may need to xacto it open for dev use, but don’t want to place a part for production), the net tie keyword removed the DRC errs:

However, for a power jumper that I use to tie analog/digital planes, or to tie an esd perimeter ring to ground, I found a subtle issue. Here are three ties; the two on the left have no drc errs since it is only the footprint, which has a fat top and bottom connection. The net tie keyword keeps it happy. The right footprint shows drc errs because I tried to improve the tie:

The reason for the drc errs is since footprints don’t allow inner layer copper (which is understandable) but my two inner layers are the main ground planes and I wanted to add copper ties there as well. Can’t do it with a track route since the pin numbers are different, but I can add a line. Now look closely and see that this disconnects the plane completely on both sides, which is hard to notice until zoomed in. That would have been a real problem if I did that on all of these jumpers and it went to production (I almost didn’t notice). The inner planes may or may not get tied through top and bottom fill-in planes with all the stitching vias but the analog plane would probably be either open or very noisy:

I tried it with a polygon (of the upper net) and it did not work when placed over the thruholes (opened at the bottom pads), but I can place it adjacent and the overlapping polygon nets result in solid copper fill, albeit with drc errs. I dunno what would be best for this. I liked it as a shorted jumper since the plane bonding is explicitly shown on both schematic and the board, but inner layers need a hack to add copper, else they only connect through the plated holes and top/bottom copper ties.

Then I tried two overlapping polygons (one of each net) and plopped them over the footprints – kinda works. Sigh.

Can you strip down the example to a minimal project and attach it here?


Hmm, I don’t know how to attach a file. I have a zip for ya.

Just drag it from a file browser into the edit window of a post.
Copy & paste also works. It’s pretty much the same as with screenshots.

Huh. For screenshot pics I used the upload button:

…and I guess that works for this attachment as well:
gnd-tie-test.zip (27.5 KB)

Oh, and when I say layer2/3, that is inner1/2 in kicad – old habits and all that.

Rule area:

Custome rule:


1 Like

I’m impressed.

I know these rules can be powerful, but I also find them pretty complicated and had not used them myself. I can reproduce eelik’s text (but I used “asdf” as name), and then both the zone connectcs, and DRC is happy. I pasted the text below, so you can also just copy it.

 (version 1)
(rule "asdf"
(condition "A.Type == 'graphic' && A.insideArea('asdf')")
(constraint clearance(min -1mm))

I also noticed the rule editor has built in syntax help:

And in the upper right corner:

1 Like

Yeah, just tried it and it worked! Crazy stuff.

I did it with ‘tie’ – what is different about ‘asdf’?

Is this rule only specific to this board then? Not something that can be embedded in the footprint?

BTW, I have to say how I really, really, really love being able to draw a polygon and click/click/click it is on other layers too. Nice.

1 Like

“asdf” is just a name I always use for “temporary stuff”.

Yes. Eeliks example made a rule area (and assigned it a name) and in the board setup you created a rule to use in that area (so the names for both have to be the same.

You can create a “rule area” inside a footprint, but I have not found an entry box for adding a rule to such an area in the footprint editor.

Here are two alternate solutions.

The rule areas are in the footprints. In the rightmost footprint the area name is “tie”. This works identically to my previous solution.

In the leftmost I modifed the pads to overlap. This is possible because by default the THT pad copper exists in all layers. The rule area name is “tie2”. Here are the rules:

(version 1)
(rule "tie"
(condition "A.Type == 'Graphic' && A.insideArea('tie')")
(constraint clearance(min -1mm))
(rule "tie2"
(condition "A.insideArea('tie2') && A.Pad_Type == 'Through-hole' && B.NetName == 'AGND' || B.NetName == 'GND'")
(constraint clearance(min -1mm))

The rule for an area embedded into a footprint must still be written specifically for each board, the rules can’t be embedded into a footprint (for natural reasons because the context is unknown).

gnd-tie-test.zip (327.3 KB)

1 Like

They are the leftmost home row keys on an English keyboard, under qwerty.

1 Like