I am not asking for footprints – I build my own and have hundreds. I understand how to do all the garden-variety stuff, but I have some footprints that are just odd, or I designed to fit multiple devices for procurement flexibility, and have drc errors I would like to not have happen.
So these two footprints are simple enough to make by adding pads with the same number, and they route just fine and DRC is happy:
Or this combo soic/vssop I need for opamps that may be in either package (and I am lucky to get either these days with the supply chain). DRC really hates the vias and traces (but it routes and works well). If I use smt pad rectangles I can hack around the trace errors, but maybe there is a better way:
They use a graphic polygon, and to make DRC happy they rely on an old hack in KiCad that uses the “net tie” keywords. Here a screenshot from: Footprint Editor / File / Footprint Properties of such a footprint:
bigfoot – funny. Soldering could be an entire thread, and maybe not appropriate for this forum, but I regularly hand solder down to 0.5mm pitch, and yeah, tacking the corners is a critical first step.
Rather than trying to hold a part’s position with tweezers or fingers when tacking a corner, a trick I use is a bit of scotch tape – stick it down on the part leaving pins on one side exposed, then grab the ends of the tape, fine-tune position to the pads, and stick the two ends to the board. The part is now not going anywhere. Check position with a loupe or such (repeat alignment as needed) and then tack a corner or two. Peel tape off and tack other side.
I have done many chips by just soldering a complete blob on all the pins on one side and using (good) solderwick to suck it off. I also have good luck by oozing a bead of flux on the pins and using an angled-flat tip loaded with solder and wiping across the whole row in one motion, many times with no shorts to wick off. Works well for any gull wing part. I have even done m.2 sockets and hdmi jacks that have exposed pins.
I also use a stencil and paste for some protos – after loading them up I fry them, er, reflow them, on an electric griddle.
A white plastic eraser is great for cleaning oxide off hasl pads on the board first but I usually get immersion gold since the chips sit much flatter and solder better.
OK, guess I have ranted enough for now
Use one or two small pieces strategically placed while initially soldering a couple of pins. The beauty of this stuff is it is still easy to adjust components. It lifts without leaving a residue, as long as you don’t leave it on the PCB for a week, and is reusable.
Keep the hot iron tip off the stuff though!
However, for a power jumper that I use to tie analog/digital planes, or to tie an esd perimeter ring to ground, I found a subtle issue. Here are three ties; the two on the left have no drc errs since it is only the footprint, which has a fat top and bottom connection. The net tie keyword keeps it happy. The right footprint shows drc errs because I tried to improve the tie:
The reason for the drc errs is since footprints don’t allow inner layer copper (which is understandable) but my two inner layers are the main ground planes and I wanted to add copper ties there as well. Can’t do it with a track route since the pin numbers are different, but I can add a line. Now look closely and see that this disconnects the plane completely on both sides, which is hard to notice until zoomed in. That would have been a real problem if I did that on all of these jumpers and it went to production (I almost didn’t notice). The inner planes may or may not get tied through top and bottom fill-in planes with all the stitching vias but the analog plane would probably be either open or very noisy:
I tried it with a polygon (of the upper net) and it did not work when placed over the thruholes (opened at the bottom pads), but I can place it adjacent and the overlapping polygon nets result in solid copper fill, albeit with drc errs. I dunno what would be best for this. I liked it as a shorted jumper since the plane bonding is explicitly shown on both schematic and the board, but inner layers need a hack to add copper, else they only connect through the plated holes and top/bottom copper ties.
I know these rules can be powerful, but I also find them pretty complicated and had not used them myself. I can reproduce eelik’s text (but I used “asdf” as name), and then both the zone connectcs, and DRC is happy. I pasted the text below, so you can also just copy it.