I want to show you and ask for a review for my new designed SoC Zynq Development Board. This board has been designed during Phils Lab “Advanced Digital Hardware Design” course.
Board features:
AMD/Xilinx Zync System on Chip (SoC) Half APU (Application Processing Unit) and half FPGA
1GB DDR3 Memory
4GB eMMC Memory
Gigabit Ethernet
USB HS OTG (USB High Speed On-the-Go) enables connectivity between portable consumer electronic devices over the industry’s most popular peripheral interface
In comparison to the original course project component selection, schematics and critical component placement this project is almost identical to the course project, however symbol library, footprint library and schematics have been done by myself in my style and all supportive components placements and layout have been done by myself in trial and error style :). It took me long hours to design this board.
I have not chosen to design my own unique project, because my hobby projects are typically much cheaper and not so advanced in layout perspective, and this board together with assembly and components are out of my hobby budget. Still, during the course and design of this project I learned a lot of new stuff and boosted my skills in HW and PCB design for both hobby and work. Although, I will not be ordering this project and wanted so share it for a review because is taken a lot of hours to complete it and maybe some of you will give me feedback with recommendations how it could be improved or take something for themselves
These are a link for Schematics, BoM, Assembly Notes, Fabrication Notes and Gerbers:
This is a very well done job, both in the schematic and pcb.
I have no real notes, just cosmetic or marketing related:
the configuration dip switch sticks out like a sore finger
completely uniform component package choice, the FTDI qfp maybe could be purchased as qfn or bga?
minor inconsistencies in the graphical representation of silkscreen (thickness, pin1 indicators)
the time of usb-otg and barrel jacks has finally come, please update to usb-pd
KiCad is looking for modern designs to add to the example directory, in my opinion this could be a nice ‘business card’ for you and for KiCad, if you can / are willing to share the sources.
mmmmmm, I dont really have time for a full review however…
Have you got enough Zynq Bypass capacitors ?
per Page 13, 14 of UG933 Zynq-7000 PCB Design Guide.
No 2.5V rail ? so I gather no LVDS options. So, no high speed interfaces.
CLK to network chip >= than all the other traces ?
First, I’m in doubt whether to respond here at all, as this sort of PCB is above my experience level. But I guess I’ll make some comments and leave the rest up to you.
As far as I know the extra “GND” / “guard ring” around the PCB with the extra via stitching has very little benefit.
10 layers also seems a bit excessive. I understand the use of multiple GND layers, but I guess this can be done on 8 or maybe 6 layers. For example Inner Layer 8 can (almost) be combined with Inner Layer 4 Both those layers do not have many signals, and the signals they do have are in different locations. but it is a tradeoff between PCB cost and designer time, and thus depends on the expected amount of PCB’s to be manufactured.
Also, the DDR routing on both the Top Layer and Inner Layer 8 are directly on top of a GND layer, while the DDR routing on Bot Layer is not. As of yet KiCad does not have propagation delay / time matching, but only length matching. The length matching “squiggles” on Inner Layer 6 is also sandwiched between two GND layers, which gives yet another propagation delay. I guess it’s better to move the DDR IC’s a bit further form each other to make more room for the length matching and then route them on fewer (but more uniform) layers.
Ambitious design! (did I read before that it’s your first one? if so, it’s doubly ambitious).
Few things that can be deduced from the PDFs:
You are using an impedance controlled design, but the stackup table (which looks nice btw) doesn’t include the Er of the materials. I assume it’s 4.5-4.6 (standard FR4). For the manufacturer, identify the layers that are impedance controlled.
for DDR3 routing, you can pin swap the DQ lines within each byte and (but please double check in Xilinx docs) the entire bytes, at least within the same chip (e.g. DQS0/DM0/DQ0-7 with DQS1/DM1/DQ15-8). This will greatly simplify your routing and you’ll need far less meanders to length match.
you seem to have too many layers for the board of this complexity. It’s also unusual to have power layer in between two GND layers. I would suggest using an 8-layer stackup of (top to bottom): signal/GND/signal/PWR1/PWR2/signal/GND/signal. Power planes serve as good reference for high speed signals (distributed capacitance + a few decoupling caps of the component are effectively a short circuit for RF). This should be sufficient for a board of this complexity. Also try staggering the first two rows of vias in the Zynq’s BGA package instead of placing them in a line - fits two tracks between each pair of vias instead of one.
Look carefully at the DDR DQS/clock diff pairs, there’s (to my taste) too much deskewing there. KiCad V7 may have bugs/inconsistencies in trace length calculations - but for this (and more review), a kicad_pcb file would be necessary.
Set pcbnew KiCad to print all vias into the PDFs (IDK if they are blind/thru).
Make sure no high speed signals (in terms of rise time, so not only DDR but also MII/MDIO/FPGA fanout) cross cuts in the power/ground planes. Also don’t cut the GND plane with long traces on mixed layers (e.g. L5).
Impedance matched traces look like they have same widths on all layers (inside/outside). Is this the case? Double-check the stackup.
R162 should be on the source side if you’re using series termination for the QSPI CLK line.
What is the dielectric type (X7R, X5R, Y5V, etc) for the 470nF/6.3V decoupling caps for the FPGA? I suggest adding a few low capacitance (1nF) but with good dielectric (C0G or at least X7R) in parallel.
I don’t know what’s the ring around the board for. Just to make it look cool?
It’s my first design of such complexity and I appreciate your feedback. I noted every feedback @twl and @glenenglish and will review my design, try to optimize it and go deeper in the Zynq manuals
The design was really challenging, but I learned from it a lot and getting good advice and feedback, so I can improve even better, is why I placed the design in this forum.
It is a nice looking board you made there. I have not looked at it in detail, but I feel the need for you to possibly reconsider the microusb connector. In my experience that is in a very fragile from factor. Think tiny connector (in “depth”) and surface mount only. If that specific connector is just there an a extra feature, ok, but if you expect to actually use the connector beware it is very fragile in my experience. Never broken one myself where I noticed, but seen countless colleagues who have turned up with boards broken.
How did you add propagation delay to your DDR signals? Did you find your own tool or something on KiCAD? I am also trying to create such designs and I have a little problem with propagation delay. I don’t know how to add
Basic maths calculations, which is giving me a bit of a headache.
First I routed traces, then I used a propagation delay calculator to find out how much I should length tune those traces. It took some time, and I have redone FPGA and DDR routing several times.
Altium would handle this much easier. But if you route everything on the same layer or keep length of parts of traces on the same layer matched, then length matching should be enough. KiCAD can do length matching.
In KiCAD there is an option to add Specify Pad to Die Length. Those delays can be found on IBIS models. I just added equivalent delay in mm to calculate the same delay time for specific pins.
