I recently finished a HDI layout using skip vias and realized that KiCad does not support skip vias at all.
I am curious if I am the first to encounter this or if anyone found a better workaround or even a solution.
For those unfamiliar with the term, a skipped via is a special type of via that is only connected to its end layers, so a skipped via going from F.Cu to In2.Cu will never connect to In1.Cu.
Skip vias can be useful when there is not enough board space to allow regular through hole vias.
See also PCB Vias: An In-Depth Guide
I managed to pull it off, but I have some advice for those who want to follow in my footsteps: be very much aware of missing ratsnest lines and missing DRC errors.
The thing is, KiCad will assume that all types of vias can connect to any intermediate layer, which can create some confusion.
My story:
My learnings begun before I realized skip vias were not supported in KiCad. The board house I used adviced me to specify the skip vias as blind vias which made some sense at the time.
In a small board area I had to use skip vias for Gnd connections and then a small Gnd pour at In2.Cu would carry the current to the nearest ThruHole via array.
After finishing the design work I noticed a lack of ratsnest lines and DRC errors for the skip vias that were not connected to anything on the internal endpoint In2.Cu because I had not yet placed the ground pour on In2.Cu.
However DRC didnât flag this because it saw the skip vias going through In1.Cu which already had a full Gnd pour so DRC assumed there would be a connection to In1.Cu - except I was going to have these vias manufactured as skip viasâŚ
So did I, but I guess we were mistaken.
The âConnected layers onlyâ option exists for the purpose of reducing stray capcitance from gigabit vias - at least that is what I have been using it for until now - there might be other use cases but it seems that skip vias is not one of them.
âSkip viaâsâ (without the âpedâ) are apparently some special feature. I did a short search and read some (parts of) articles. The link below is one of the better explanations.
I also did a search through the Gerber X3 standard. It has four references to skip but all are in a different context. Maybe this is only defined in those âotherâ pcb manufacturing formats? As far as the Gerber standard is concerned, there is only a start and a stop layer for holes (PTH, Blind, Buried), and there is no specification on how the hole is made.
So maybe it is the same. If KiCad removes the annular rings, then the PCB manufacturer can deduce that skip vias can be used.
The Annular rings setting controls which layers will have annular rings for the via.
When set to All copper layers, the via will have annular rings on every layer.
When set to Start, end, and connected layers, the via will have annular rings on its start and end layers as well as any layer with a track or zone connection to the via. Any layer without track or zone connections, other than the start and end layers, will not have an annular ring.
When set to Connected layers only, the via will have annular rings only on layers with a track or zone connection to the via. Any layer without track or zone connections will not have an annular ring.
When set to Start, end, and connected layers , the via will have annular rings on its start and end layers as well as any layer with a track or zone connection to the via.
Exactly, which is why I said kicad doesnât support it.
Now, I am skepical of what benefit is gained by tunneling through a GND plane without connecting in order to reach the same net on a deeper layer. But that is what OP is trying to accomplish.
Youâre right, I just edited title and text to remove âpedâ
I also did a search through the Gerber X3 standard. It has four references to skip but all are in a different context. Maybe this is only defined in those âotherâ pcb manufacturing formats? As far as the Gerber standard is concerned, there is only a start and a stop layer for holes (PTH, Blind, Buried), and there is no specification on how the hole is made.
Interesting, I would definitely have thought that skip vias was part of Gerber spec
So maybe it is the same. If KiCad removes the annular rings, then the PCB manufacturer can deduce that skip vias can be used.
In that case, even if the extra annular rings are removed there is still a gap in how kicads DRC handles this special case. An acceptable solution would be that an intermediate zone are to keep a clearance to the skip via even when they are on the same net.
Yep I get that . . . . but there is a distinction to be made about what KiCad is meant to do . . . and what it doesnât support.
If itâs meant to do it and it doesnât then there is a bug and it needs to be reported . . . if itâs not supported, i.e. not meant to do it, then there isnât much to do other than hope it get added.
Now, I am skepical of what benefit is gained by tunneling through a GND plane without connecting in order to reach the same net on a deeper layer. But that is what OP is trying to accomplish.
You scepticism is fair. To begin with, lets just say itâs complicated. I guess this could be considered slightly offtopic - but here goes:
It is a high density complex design with very little space available for Thru-Hole vias because of features on the opposite side of the board. My board house offered me this stackup which meant that I could use the little space available for various power rails coming in from inner layers deeper within the stackup, the tradeoff being that In1.Cu would be unused in the affected area of the board. I managed to do approx. 90% of the routing between pads on the outer layer and 10% using thin short traces on In2.Cu. As a result of this I ended up with two separate ground layers in the affected area.
Skip via is just a blind via that cannot connect to intermediate layers. They are faster to manufacture than stacked or staggered microvias because this technology requires fewer lamination/plating processes
