Simulations for IC-Design with NGSPICE


I would like to evaluate if a circuit design would benefit if I would made an IC instead of a circuit with discrete components. Since the interface of eeschema is quit comfortable I would like to use the KiCAD environment for the simulations. However, independent of the interface to ngspice, I need the component parameters for the simulation. Usually foundries provide PDK being compatible with cadance, mentor and ADS. Is there any chance for ngspice to access these information too?

I found the homepage coorperating with the google skywater technology. But to my understanding they are focusing on digital design and I would like to do some analog simulations e.g. for a x-fab technology.


You will need to ask X-Fab to get access to their PDK. ngspice then will be able to handle it (proven with some 0.18um process).

Sure I have to ask them, but how does the interface between ngspice and the PDK works? I already saw PDKs from STM and IHP and they did not include a lib-file with spice code which could be used to generate a library representing the components of the process.

You may ask to obtain a HSPICE compatible simulation support. ngspice should be able to read this.

Some more info on IC-parameters for simulation is available on the ngspice model parameter page.

I have been playing around a little with the IC design style (simulation only) for CMOS, using KiCad-5.99. Attached you will find a possible solution as a zipped project.

I have created 2 new symbols, PMOS and NMOS. Both transistors have 4 terminals, as required in IC design: drain 1, gate 2, source 3, and bulk 4.

With the symbol editor I have added 4 additional fields, which are normally created only during attaching a Spice model to a symbol. For example for the NMOS:

Spice_Primitive             X
Spice_Model                 NCH W=1 L=1
Spice_Netlist_Enabled       Y
Spice_Lib_File              cmos_sub.mod

So these fields are already integrated into the symbol which is stored in the (private) symbol library. Thus the user does not need to attach a Spice model each time he or she places a new device into the circuit diagram. The only thing to do is to edit the Spice_Model line for an adequate W and L (given in m, for example W=2u L=0.5u).

The new symbols are stored locally in the private library CMOS.kicad_sym and are referenced with a relative path in sym-lib-table.

The file cmos_sub.mod allows access to the model parameters for the MOS devices. It contains 2 subcircuit models for NMOS and PMOS. Each model calls the MOS primitive, but also performs some area calculation for drain/source capacitors. The original Spice model parameters are referencing the Berkeley BSIM3 MOS model, which is adequate for conservative CMOS down to 0.35um channels (modelcard.pmos, modelcard.nmos). The data stem from Berkeley’s original model development and are not describing a real foundry process.

The circuit is simple: a CMOS inverter, driven by a pulsed voltage source. It uses global labels for naming some nets (o.k. because we do not generate a PCB, and their net names are not modified).

If running the simulation, do not set Sim Parameters --> Compatibility Mode to LTSPICE or PSPICE, because then the BSIM3 models may not be referenced adequately.

ngspice also offers the BSIM4 MOS model, which is o.k. down to 45 nm or so. You just need to have access to suitable model cards (see the link given in a previous post). (10.1 KB)

Following is a slightly more complex example, a two stage CMOS operational amplifier according to the paper , using the CMOS symbols as described above. (34.3 KB)

The circuit diagram (Eeschema screenshot) looks like

Edit: Fix a bug (exchange in+ and in-)


Franzee, do you have (or will provide) a KiCad symbol library with the bipolar symbols?

Meanwhile I have been working on an update of the CMOS symbols for IC design.

Attached you will find another example, the CMOS 555 circuit (Fig. 11.9) from Camenzinds book.

However I have not created MOS symbols with only three pins. Why not?

The integrated MOS device is a true 4-terminal device. The designer has always to consider that the transistor may also be controlled by a backgate voltage (voltage between bulk and source).
And all foundry models for MOS are 4-terminal models.

I am not yet completely satisifed with the symbols. You have to enter W and L twice, for the printout and for the model. I have not yet found a better way to make the printout compact. The position of the printouts (Transistor instance, W, L, (and M)) is somewhat erratic. The nice picture has required some manual movement.

The project is (86.9 KB)

The simulation shows the oscillation starting after some start-up time.