Simulation Workflow Best-Practise for a Complete Project

Hi!

I’ve been trying simulations with KiCad 8, and have managed to simulate a small circuit. Now I’m curious about how to incorporate simulation into a larger project.

A complete project schematic may have some things that cannot be simulated. I can stub out 2-pin connectors easily enough (by giving them a simulation model of a capacitor set to 0.01pF for instance!). But there may be larger bits of circuitry that I do not want to simulate.

After playing around a bit, I have a proposed workflow. I don’t know if I’m missing a better method however, so I’d be interested in hearing feedback. Here is what I believe works, and is fairly reasonable:

(1) Start a project, and whenever there is a portion of circuitry that one would like to be simulated, cut-paste it into another sheet in the hierarchy. Then connect the sheets as usual using the root level sheet.
(2) When you’re ready to simulate an individual sheet, close the project, then using the normal Windows file explorer, right-click on the individual sheet filename, and select Open With->KiCad Schematic Editor 8.0 and then run the simulation. In effect, you are simulating the schematic sheet outside of the project.

Although the above works, maybe a slightly better workflow modification (which I have yet to try) would be to have at least three layers in the hierarchy, so that simulatable sub-circuit sheets are placed at the lowest layer, and can be connected together in the middle layer, so that they can all be simulated together. The topmost layer is the one that is not simulated.

What do you think? Is this a reasonable proposal, or is there a better way to either stub out or providing a mock function for areas of the circuit that are not simulatable?

Many thanks!

I have never need to simulate complete project.
Whenever I simulated something it always was a small sub-circuit I had some doubts how it works (mainly supply filters with all element modeled including parasitic components (C + ESR + ESL and so on).
In KiCad I have separate configurations (with separate library sets) for PCB design and for simulations. Symbols in PCB design libraries don’t have models but have footprints and symbols in simulation libraries have models but don’t have footprints.

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I really like having ngSpice integrated into KiCad. For me it’s the difference between not using any sort of simulator myself, or trying to make the simulator work to see if I can apply it in some useful way. Up to now I have made only one simulation that actually resembles a real circuit I want to build and that was a very small part of a bigger project.

Most often it also does not make sense to want to simulate a whole circuit, and you just want to simulate small parts, such as an ADC buffer stage (without the ADC itself or the digital stuff behind it)

Advantages for ngSpice being integrated into KiCad is that it uses the same user interface, and the same libraries, so I do not have to learn another user interface (which is a real *&^%$#@! for me). And because it’s the same program, it’s also easy to copy a (part of) a schematic to another project for simulation, or as you wrote, re-use a sheet in a project especially made for the simulation.

It would be nice If I could limit the simulation to only a single sheet of a hierarchical project, or even draw a rectangle on a sheet and then only simulate the stuff inside that rectangle. But as far as I know there is nothing built into KiCad (yet) to do such a thing.

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Thanks for the feedback @Piotr and @paulvdh
I too don’t wish to curently simulate the entire project, simply parts of it, but to be able to still have the simulated parts of circuit in sync with the project. Each sheet is simulatable in isolation, by closing the project and only opening a single sheet using the KiCad schematic editor program, so I’ll continue to pursue that technique, and see if I can create an entire project around that method. I may hit other issues, but I guess it’s worth a try.
Thanks again for the responses.

Me too, I really like having it integrated. The simulation improvements in 8 were fantastic but it also made me wish for more :slight_smile:

I have specific sheets with different things to simulate. Then I basically go into each sheet and do ctrl+a, right-click then attributes->exclude from simulation. Then I go to the sheet I’m interested in and include it for simulation. It works, but it’s a bit annoying.

This seems to be the ticket where it’s tracked

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Thanks for the info! I didn’t realize there was an attributes->exclude from simulation. I see it now. I can see that would get irritating fast though, having to keep an eye on what’s excluded and what’s included each time it is desired to simulate a single sheet out of a many sheet project. But at least it’s a solution. I will use it for definitely excluding the top-level sheet since I won’t want to simulate that.

For some future KiCad version, scripting for inside the schematic editor is planned. When that is implemented, it is probably simple to write a script to manipulate the “Exclude from simulation” flags to limit the simulation to a single sheet or even some other specified sub section.

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V.8.99:

image

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Waauw, that’s nice.
Same attributes as for symbols, but now for a whole sheet.

I’ve had some projects, in which a part was a PCB, and a part were big steppermotor controllers and other stuff on a DIN rail. Being able to exclude that with a single checkbox for that sheet is nice too.

The post-v8-new-features-and-development-news is currently at 43 posts (roughly equals new features) and this is not even mentioned. I guess some (a lot of?) the smaller improvements do not make it to that list.

eelik, that is nice to see. I assume it’s just a sheet override without altering any excludes/includes in the sheet itself? Do you know if it’s also possible to select subsheets on the root page and set those attributes in one go?

Would have been nice to have a “Run Simulation of Current Sheet” button in the simulator. Then I won’t have to do fiddle around with excludes once they were set.

It was mention very briefly on 29th of june. I just found it 15 minutes ago after reading eeliks post. No wonder I missed it first :slight_smile:

One thing that would be nice to see is some configurability on the simulation charts, they are quite hard to read due to the tiny text.


The workaround is to save as CSV and create in (say) Matlab or Python.

Hm, maybe the ability to run a user Python script to allow custom formatting would be pretty neat! Anyway, this is unrelated to the topic, just thought I’d mention it in case there’s a better solution that I’m not aware of.

The discussion in this thread is also related to this discussion:

Also, these two issues are relevant:

and:

See here: Sim behaving unexpectedly, seems to be related to Hierarchical labels - #13 by shabaz
(search for the text sim_select) for a solution of sorts.

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