I’ve been tinkering with a simple filter synthesis utility (at https://github.com/bson/filtergen, but it’s still very much in an exploratory phase) that outputs .sch files that can be appended to schematics. If I add a voltage source for the input, and a couple of voltage sources for the rails, and then try to simulate e.g. the reference stage circuit (see the repo readme for a screenshot) I get the following errors:
Circuit: KiCad schematic
Error on line 8 : u1 net-c3-pad1 net-c3-pad2 0 vss 0 net-c4-pad2 net-c4-pad1 vdd lm358
Unable to find definition of model vss - default assumed
unknown parameter (net)
Error on line 14 : u2 vout net-c7-pad2 0 vss 0 net-c8-pad2 v1 vdd lm358
Unable to find definition of model vss - default assumed
unknown parameter (net)
Background thread stopped with timeout = 0
Doing analysis at TEMP = 27.000000 and TNOM = 27.000000
No. of Data Rows : 0
I’ve added a model for the LM358 just for simulation purposes. But if I understand the messages correctly, it looks like the power nodes vss,vdd are output as components and there is no model for these parts, rather than as nets with the names vss,vdd.
Is there something my program can add in a field to indicate these are to be treated as labels (net names) rather than components? I do notice the spice parameters are stored in the user F rows for components. Alternatively, is there a dummy component model I can use as a workaround?
When synthesizing a filter I want run a baseline simulation on the calculated passive component values to eyeball it for correctness. I’ll then proceed to change component values into standard, obtainable values, and rerun the simulation. At this point I want to see the difference between the two plots; ideally in the simulator itself (for example by saving the baseline and subtracting it, or plotting one on top of the other), or by storing the data to files and doing it myself. When realizing the physical circuit I want to pull trace data off my VNA and again compare. So an important function would be to save simulation plots to files. (I just mention this as a strongly suggested use case. I understand perfectly well it’s a work in progress; if I could manage to build KiCAD on OSX I’d look into adding it myself.)
Anyway, just a question and a suggestion. I’m using an OSX nightly about a week old. (I don’t see any commits that suggest any of this would be different, and besides it’s not really a bug report but more asking for how to go about running simulations with minimum legwork.) ngspice-27, although I just built and installed ngspice-28 (as a dylib) but haven’t checked it out yet.
Oh, and are there any plans to add schematic synthesis plugin support? I think something like this would be much more usable without having to go through the whole append schematic detour.
Here’s what the simulated circuit the above message relates to looks like… simulation.png