I think you should put the 2 inputs: Set and Reset, in a high state all time (Not with pulse source or connected to clock signal), so you can observe the output Q, with the Data and Clock inputs much more clearly.
Create a (pure digital) subcircuit for the single stage with the flipflop, which may comprise of 2 codemodel D flipflops.
These already have asynchronous set/reset inputs. I guess one should use the slave stage to provide the parallel input for D0 to D7.
Use exactly the same glue logic as shown in the data sheet’s circuit diagram (2 inverters and two ANDs per stage).
Cascade the 8 stages.
Add the clock (CP) and parallel load input (PL) glue logic (3 inverters, 1 NAND).
Add the ADC and DAC interfaces to each input or output (the 14 pins to the outside world). VDD and GND would not be used for the interior circuit. VDD however might be set as a parameter to set the (analog) output levels and some voltage depending timings.
Put the whole thing into a subcircuit.
The interesting question might be how to translate the dynamic (timing) characteristics from the data sheet (p. 6) to the code model delay parameters.