Simulate Shift Register in Ngspice

Schematic Simulation (Ngspice)
1

Hello im really new to simulating. I have the following circuit i want to test:

Screenshot 2020-11-28 at 18.22.37
Screenshot 2020-11-28 at 18.22.372586×946 180 KB

There is a 4021 8-bit static shift register in the symbols. But i can’t find a model for it.

Also i tried to creat my own shift register using D Flip-Flop 74HC74 with this model:

*SRC=74HC74
*SYM=74HC74
.SUBCKT 74HC74 1 2 3 4 5 6 7 14
*1=CLR 2=D 3=CLK 4=SET 5=Q 6=Q\ 7=GND 14=VCC
* 20=Momentary Clock 21=Q before RC 22=Q after RC 23=VCC that we can look
R1 14 23 1
R2 14 20 1
R3 21 22 1
C1 3 20 0.0000001 IC=0
C2 22 7 0.0000001 IC=0
B1 21 7 V = {IF( (((V(1,7))<((V(23,7))/2)) + (((V(20,7))<((V(23,7))/2)) * ((V(2,7)).  <((V(23,7))/2)))), 0, {(IF((((V(4,7))<((V(23,7))/2))} + (((V(20,7))<((V(23,7))/2)) * ((V(2,7))>((V(23,7))/2)))), V(23,7), V(5,7))) )}
B2 5 7 V = {IF((V(22,7)<(V(23,7))/2),0,(V(23,7)))}
B3 6 7 V = {IF((V(5,7)>(V(23,7))/2),0,(V(23,7)))}
.ENDS

I’m trying to test only one FF but it behaves really weird in a way that the V1 and V2 pulses are destroyed. ( CIRCUIT IN COMMENT)

So questions are:

  • Is there any model for 4021 8-bit static shift register?
  • What is the proper way to simulate and test a D Flip Flop? What I’m doing wrong?

Thanks !

2

*CIRCUIT:

Screenshot 2020-11-28 at 18.29.06
Screenshot 2020-11-28 at 18.29.061513×621 7.62 KB

3

I think you should put the 2 inputs: Set and Reset, in a high state all time (Not with pulse source or connected to clock signal), so you can observe the output Q, with the Data and Clock inputs much more clearly.

6

Have you tried the PSPICE model for the SN74HCS74 directly from Texas Instruments? Maybe you’ll get different results???

Direct link to the archive here:
https://www.ti.com/lit/zip/scem774

Additionally, you can check this file out. It has its own 74HC74, but also the 74HC165 which is [mostly] equivalent to your CD4021.

https://github.com/texane/power_inverter/blob/master/ltspice/logic/74hc/74hc.lib

7

Some ideas how to generate a ngspice model for the 4021:

There is a very nice circuit diagram on page 2 of the NEXPERIA HEF4021B data sheet (https://assets.nexperia.com/documents/data-sheet/HEF4021B.pdf).

Each of the 8 shift register stages contains an edge triggered master-slave D flipflop (https://www.sciencedirect.com/topics/computer-science/master-slave-flip). Each stage has an asynchronous parallel data in.

Create a (pure digital) subcircuit for the single stage with the flipflop, which may comprise of 2 codemodel D flipflops.

These already have asynchronous set/reset inputs. I guess one should use the slave stage to provide the parallel input for D0 to D7.

Use exactly the same glue logic as shown in the data sheet’s circuit diagram (2 inverters and two ANDs per stage).

Cascade the 8 stages.

Add the clock (CP) and parallel load input (PL) glue logic (3 inverters, 1 NAND).

Add the ADC and DAC interfaces to each input or output (the 14 pins to the outside world). VDD and GND would not be used for the interior circuit. VDD however might be set as a parameter to set the (analog) output levels and some voltage depending timings.

Put the whole thing into a subcircuit.

The interesting question might be how to translate the dynamic (timing) characteristics from the data sheet (p. 6) to the code model delay parameters.

8

Unfortunately the cited library cannot be used with ngspice, because it contains non-compatible A device models.

9

Gotcha. So they need to be modified to work with ngspice’s A-devices, which is what you did with the handful of gates found in the 74HCng.lib.

Anyway, sounds like the above procedure is what the thread author wanted to do initially, but got hung up on the Flip-Flop.