Simulate on the TPS57140-Q1_TRANS of TI

I am trying to simulate on the TPS57140-Q1_TRANS of TI under both kicad V6 and console mode, but always stop at the “Timestep too small” problem and just wondering how to fix it. can someone help on it? Many thanks!

doAnalyses: OP: Timestep too small; trouble with xu1.x_u30:smoothsw-instance s.xu1.x_u30.s5

vsim.cir (1.1 KB)
ucc28c43_trans_unencrypted.lib (13.6 KB)

I must say that my understanding of the Spice simulation is far from complete, but this timestep too small error seems to indicate that the system you try to simulate can not be solved properly. It might be for a variety of different reasons, and the fault is not always in the component indicated, or at least the solution is not necessarily there.
It could be a problem with the model, or the circuit has some other problem that causes this.
I usually make a very simple and small test circuit with the component I suspect, or when I have trouble with a model, just to check that it works as expected and I have connected the pins correctly, as pin numbers in KiCad symbols and models often do not match.

You are talking about the above model but have added a different library model. And this *.lib file contains three or more models of the same circuit, probably for different simulation types. So this alone does show that simulating a switch-mode power supply is not an easy thing.

To try to obtain convergence, one might start playing with simulator options, either for the operating point or the transient simulation. Some succes might be possible with the following setup (standard ngspice):

V1 VIN 0 dc 0 pulse 0 12 0 0.5m 0.5m 1 1
.option chgtol=1e-11 reltol=0.01 vntol=10u
.tran 120n 12m

iplot v(/vout) v(/RT_CLK) V(VPH)
plot v(/vout)

So ramp the power supply from 0 to 12 V. This eases finding the operating point. chgtol=1e-11 sometimes allows better transient convergence. reltol=0.01 vntol=10u (relaxed tolerances) may be set when the simulated voltages are higher than the usual 3.3 V for ICs.

Unfortunately still then, when looking at VPH, there is small needle pulses only, but no pulse width modulation to raise the output voltage. More analysis of the inner workings of the model may be needed.
o0oke.7z (7.8 KB)

The “timestep too small” is just one of many completely meaningless error messages that ngspice is able to generate. It means nothing at all and is not helpful in any way.
In my experience, it can have something to do with pin/node sequencing, reverse polarity, operation outside limits, basically anything.
Sorry, but you’re on your own here.

ML9104, unfortunately your contribution in your last post is wrong and not very helpful.

There is lots of literature about the message “Timestep too small” in a spice simulator.

The message “you’re on your own here” is absolutely wrong.

ML9104, obviously you did not check my last post, nor did you run the circuit yourself to help the OP. With my suggestions the “Timestep too small” message is gone.

Unfortunately the simulation then does not yield a suitable output voltage, instead the output goes to 0. This may be a model bug in the TI model, as other users have experienced the same issue with the TINA simulator, as discussed in .

You’re right insofar as the error message itself is not very helpful. I listed some of my experiences as to the origin of this kind of error, and it’s to the point. It goes back to my frustrations getting simple simulations to work and constantly getting this “brainless” error.
It makes people sit for hours and diddle around with changing the step size in the simulation. Why?
The error message tells you nothing. So why print it? “Simulation failed” would be just as informative, but users are being led up the garden path instead.

I think our replies crossed each other, and that I didn’t see your reply before posting. That happens, sorry about that.

That you’re able to suggest corrective measures is great, I applaud you.

Thanks All,
I am agree with you @hmk , but not sure how to check on the pin match with Kicad symbol correcetly or not. we need a detail flow or a example, for guiding user to fix this kinds of mismatch problem. the alternate node sequence adjustment might be a good direction but I am not sure how to setup it.

Thanks @holger I try the option your suggestion, and I can run the flow, but finally the VOUT not match with PSPICE result of Orcad which I am not sure realtive to the reason of the rise time different between the two simulation tools? Pspice the VPH raise much more faster than ngspice.

Thanks @ML9104 , for a tool, the output can be improved on better guiding user, we can make it more better by sharing different solution on the same problem and then feedback to developer on optimization, let’s make it better.

There are so many reasons possible to provoke this failure, so it will be necessary that your brain to become activated. Search the web for possible reasons for this specific message, or grab a book on Spice to figure out what might have happened.