I’m laying out a board with a dedicated ground layer with a copper pour that covers the entire layer. All SMT device pins that need a connection to ground have their own via located next to the pin. With this setup I saw no need to connect each of the vias to each other on the ground layer, leaving it to the pour to make the connections.
While researching I came across several discussions on the 'net where “experts” insist that pours shouldn’t be used for connections. Instead, they claim each via needs to be explicitly routed on the ground layer, and only then should a pour be flooded over the layer for lower impedance, etc.
Is there a good reason do this? Assuming no DRC errors and no unrouted nets after the pour, can a pour be trusted to connect to all vias of the same net? If not, why not?
I do not understand what you mean here, and I am probably not the only one. Of course, the vias are connected to each other if they are all ground vias connecting to the pour on the ground layer. How are they not connected?
I mean they claimed that you should route tracks connecting the vias and then pour the layer over these tracks, rather than depending on the pour to connect the vias.
I’ve seen pours that barely sneak though two pins, so that might be a worse connection than explicitly routing a path. But, generally those cases are obvious, and they can be fixed by shifting components. If they can’t be fixed, a trace isn’t going to make it between those pins either…
OK another important variable is whether you are using thermal reliefs? I think those should not be needed on vias (as opposed to through hole pins) but I generally do not use thermal reliefs anyway.
Running traces and pouring over them seems like unnecessary redundancy IMHO.
Personally I route as normal and treat the pour as a bonus for the ground plane. For my hobby circuits involving milliamps I doubt if it makes any difference.
@RRPollack
There is a good reason to route GND pathes within a GND poor.
In RF designs, or where high dt/dv signals are involved, special care has to be taken for GND routing. It is a complex matter. One major aspect is EMI.
One little peek into this world of voodoo:
In RF or fast switching signals, the GND current does not spread into the GND layer, as you might expect. Instead, it sticks to VCC track on the other layer, just where it came from! Magic!
So to keep control of effects and sideeffects, it is of advantage to route GND tracks even inside a GND poor.
BUT: this is a very special matter, in many cases you do not need to worry about that.
In short: Any GND connection generated by a poor will have connection to GND, no worries.
In pro-designs and RF designs you need deeper studies about that matter.
Yes, there is some truth in the sentence.
Consider that: you don’t have strict control over the way that the pour is shaped, for example it could happen that some connected islands are generated.
All results ok from the DRC point of view but as pointed out, for controlled impedance or fast switching signals the return path is as important as the signal track itself and relying on the pour in certain cases could not be enough.
Copper pours are easily shoved around when laying tracks with the Interactive router, and in some area’s this can break connectivity. When copper pours have a thin section surrounded by tracks (Most often this happens on dual-layer boards, where GND has to be stitched together) I add some tracks through the pour to ensure connectivity is always ensured. But I only to that in those area’s. When there is no risk of a section of a pour becoming disconnected, I just rely on the pour itself.
I think it’s nonsense, what you see in PCB is a graphical representation. if you have two connections to GND within a GND pour there is zero point in connecting them, they are pixels.
unless something got lost in translation
That is very true. But the copper on the board is the same regardless of whether there are redundant tracks (or redundant tracks) buried in the copper zone in KiCad and the Gerber files.
UNLESS your copper pour (copper zone in KiCad speak) is not solid. If your copper zone is a grid or something with open areas in it, then there would seem to be the chance of a functional difference.
That is often true, but in this case there is a right answer and its simply ‘Yes’ at the risk of going all Zen on you but the copper that will form your next pour on your next PCB is probably sitting in a Chinese warehouse already attached to a piece of FR4 and all Kicad can do about that is reduce its surface area, so two GNDs within one pour do not need to be connected. But if you want to see pictures of the project thats great as its your time !
From the description we don’t know what is meant. There are two viewpoints: 1) general design principles and laws of electronics, and 2) how the used EDA sw works.
If we take an example where the return route is critical for some tracks, we can say that in principle we should make sure the ground plane is continuous under the track. Using vias and refreshing the zone in KiCad doesn’t guarantee that. Routing with explicit ground track and locking the track would do that, assuming that the ground track is always updated when the signal track is changed. It would also guarantee minimum track width in that route, in case the minimum zone width happens to be smaller (if that matters at all).
I wonder if any EDA package has some way to check return paths, or for example automatically drawing a track in a plane under the explicit signal track.
Mousey seems to have a third viewpoint but I can’t quite get what it is.
My viewpoint is simple, the quote above is nonsense, our OP is being told that two points on the same layer and the same net need to be physically routed visibly with a trace and then a pour is applied suggesting the trace is somehow still contributing to the physics of current flow. I can not subscribe to that. Planes under explicit tracks are a whole new board game and has not been mentioned. I personally trust Kicad to handle simple pours so thats the answer to the OP’s question from me anyways
I agree with some of the commonsense comments and different situations dictate ‘what’ and ‘how’ something could-be/should-be done.
There is No ‘One’ specific answer that applies to all situations.
That said, if you can draw-it, lay-it-out, NET-it, hook-up connections to components/pads/pins/wires, then the only remaining significant issue(s) are:
• does it make good engineering sense
• can it be built
• are you willing to ignore or setup DRC warnigs/errors
Below screenshot shows 4-Layer PCB with GND-Plane on Bottom Layer.
Some components connected to it, including Vias, a Ground Wire and a Screw-Terminal-Post.
Top and Btm views show the related items poking through the Btm waiting to be Soldered… The Red Arrows and Circles indicate the Vias and Btm Pad (that are Contiguous with the GND-Plane). You can see the other Pads that are Not assigned to the GND-Net and are thus, isolated from the GND-Plane…
Thanks to everyone who has taken the time to respond!
Let’s see if I can summarize the answers:
Assuming no DRC errors or unrouted signals, a poured plane will connect to all vias of the same net within the boundary of the pour.
For DC or low frequency and slow slew rate signals, there is no requirement to connect vias within the plane separately from the plane pour.
For high current vias or pads, the robustness of the connection between the pour and pads or vias should be examined, especially when using thermal reliefs in the pour.
For high frequency or fast slew rate signals, special attention must be paid to the path a signal and its return will take. There may then be an advantage to placing a track through the pour area before filling it, as this may help visualize where this path is, and may be more resistant to being interrupted inadvertently.
Always watch your bartender when they’re pouring your drink.
It’s likely (but not certain) that if you have to ask it’s probably doesn’t matter. If it does matter (in your specific application) then you really shouldn’t be asking here
